LVDS receiver circuit

Details LVDS receiver circuit LVDS receiver circuit

2007-10-05

2009-12-29

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C327S066000, C327S067000, C327S109000

Reexamination Certificate

active

07639043

ABSTRACT:
The LVDS receiver circuit comprises a differential-input transistor pair, a control transistor pair, a current-mirror-load circuit, a first feedback inverter and a second feedback inverter. The first feedback inverter, the second feedback inverter and the control transistor pair constitute a feedback loop. The voltage change of the input voltage of the first feedback inverter is suppressed, and the input voltage is controlled around the threshold voltage of the first feedback inverter.

REFERENCES:
patent: 5666068 (1997-09-01), Ehmann
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 6452429 (2002-09-01), Lim
patent: 6512400 (2003-01-01), Forbes
patent: 6788142 (2004-09-01), Li et al.
patent: 6879198 (2005-04-01), Kumar et al.
patent: 7199638 (2007-04-01), Dubey et al.
“Delay and an Inter-Bank Shared Redudancy Scheme”; Digest Of Technical Papers; pp. 418-419 and 487 (1999 IEEE International Solid-State Circuits Conference).

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