LVDS output buffer pre-emphasis methods and apparatus

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S030000

Reexamination Certificate

active

11189348

ABSTRACT:
Methods and apparatus are provided for performing pre-emphasis of signals using buffer circuitry that is not dedicated to LVDS transmission. In an embodiment of the invention, pre-emphasis circuitry is provided to enable unused transistors of the buffer circuitry to increase the current that can be driven onto output signal lines, resulting in sharper signal transitions and improved signal integrity. In addition, circuitry can be provided that limits the duration of the pre-emphasis to a selected period of time, thereby conserving power and limiting the differential voltage between a given pair of transmitted signals.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3633120 (1972-01-01), Battjes
patent: 4333058 (1982-06-01), Hoover
patent: 4527079 (1985-07-01), Thompson
patent: 4658156 (1987-04-01), Hashimoto
patent: 4723110 (1988-02-01), Voorman
patent: 4797631 (1989-01-01), Hsu et al.
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5059835 (1991-10-01), Lauffer et al.
patent: 5067007 (1991-11-01), Otsuka et al.
patent: 5144167 (1992-09-01), McClintock
patent: RE34808 (1994-12-01), Hsieh
patent: 5420538 (1995-05-01), Brown
patent: 5491455 (1996-02-01), Kuo
patent: 5521530 (1996-05-01), Yao et al.
patent: 5557219 (1996-09-01), Norwood et al.
patent: 5589783 (1996-12-01), McClure
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5742178 (1998-04-01), Jenkins, IV et al.
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 5801548 (1998-09-01), Lee et al.
patent: 5936423 (1999-08-01), Sakuma et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6040712 (2000-03-01), Mejia
patent: 6175952 (2001-01-01), Patel et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6281715 (2001-08-01), DeClue et al.
patent: 6288581 (2001-09-01), Wong
patent: 6292014 (2001-09-01), Hedberg
patent: 6373278 (2002-04-01), Sung et al.
patent: 6377076 (2002-04-01), Gauthier
patent: 6433579 (2002-08-01), Wang et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 6750675 (2004-06-01), Venkata et al.
patent: 6854044 (2005-02-01), Venkata et al.
patent: 6940302 (2005-09-01), Shumarayev et al.
patent: 6956407 (2005-10-01), Baig et al.
patent: 6977525 (2005-12-01), Komatsu
patent: 6985021 (2006-01-01), Zaliznyak et al.
patent: 2003/0141919 (2003-07-01), Wang et al.
patent: 2004/0140837 (2004-07-01), Venkata et al.
patent: 2005/0095988 (2005-05-01), Bereza et al.
patent: 2005/0160327 (2005-07-01), Baig et al.
patent: 0 575 124 (2001-05-01), None
U.S. Appl. No. 10/756,949, filed Jan. 13, 2004, Kwasniewski et al.
U.S. Appl. No. 10/937,518, filed Sep. 8, 2004, Wang et al.
U.S. Appl. No. 10/962,137, filed Oct. 8, 2004, Wang et al.
B. Gilbert, “The Multi-Tanh Principle: A Tutorial Overview,” IEEE Journal of Solid-State Circuits, vol. 33, No. 1, Jan. 1998.
“Block Diagram for NSM LVDS Output Buffer,” “Circuit Trace from National Semiconductor Device,” National Semiconductor Corporation, no date.
K. Farzan, “A CMOS 10-Gb/s Power-Efficient 4-PAM Transmitter,” IEEE Journal of Solid-State Circuits, vol. 39, No. 3, Mar. 2004, pp. 529-532.
“LVDS Owner's Manual; Design Guide,” National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7, no month.
“ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01,” Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
“Optimized Reconfigurable Cell Array (ORCA), OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief,” Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
Patel, R. et al., “A 3.3-V Programmable Logic Device that Addresses Low Power Supply and Interfce Trends,”IEEE 1997 Custom Integrated Circuits Conference, May 1997, pp. 539-542.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note,” Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6, no month.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31),” Xilinx Corporation, Oct. 21, 1998, pp. 1-14.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0),” Xilinx Corporation, Oct. 20, 1998, pp. 1-24.
“DY6000 Family, FAST Field Programmable Gate Array, DY6000 Family Datasheet,” Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

LVDS output buffer pre-emphasis methods and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with LVDS output buffer pre-emphasis methods and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LVDS output buffer pre-emphasis methods and apparatus will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3781795

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.