LSI system capable of reading and writing at high speed

Details LSI system capable of reading and writing at high speed LSI system capable of reading and writing at high speed

1999-04-06

2002-03-12

Yoo, Do Hyun (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S004000, C711S154000, C711S110000, C710S022000

Reexamination Certificate

active

06356976

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system Large Scale Integration (a System LSI) formed on a single semiconductor chip, in which a micro processing unit (a MPU) and a control LSI that may operate independently are formed.
2. Description of the Related Art
FIG. 1
is a diagram showing the configuration of a conventional LSI system. In
FIG. 1
, the reference number
1
designates a MPU having various kinds of units such as a CPU
3
, and the reference number
2
denotes a control LSI having various kinds of units such as a data interface circuit, that may operate independently from the operation of the CPU
1
. Hereinafter, this control LSI is referred to as a Hard Disk Controller (HDC). The reference number
3
indicates the CPU in the MPU
1
, the reference number
4
designates a code interface unit (hereinafter, referred to as a CIU) for reading program codes stored in a Read Only Memory (ROM)
7
or a Static Random Access memory (SRAM)
8
, the reference number
5
denotes a ring buffer as a FIFO buffer for storing the program code read from the ROM
7
or the SRAM
8
, and the reference number
6
designates a Data Interface Unit (hereinafter referred to as a DIU) for reading data stored in the ROM
7
or the SRAM
8
or a register
9
and for writing data into the ROM
7
or the SRAM
8
or the register
9
. The reference numbers
7
,
8
, and
9
denote the ROM, the SRAM, and the register, respectively. The reference number
10
designates a control Unit for the HDC
2
(hereinafter referred to as a HDC
13
CU). The reference number
11
denotes a data interface circuit for accessing a ROM
13
, a SRAM
14
, a register group
15
including a plurality of registers such as a register
15
a
and a register
15
b
, and a DRAM
16
. The reference number
12
indicates a DRAM controller (hereinafter referred to as a DRAMC) for controlling operation of the DRAM
16
. The reference numbers
13
,
14
,
15
,
15
a
, and
15
b
designate the ROM, the SRAM, the register group, the register, and the register, respectively. The reference number
16
denotes the DRAM, and the reference number
17
indicates a bus group through which data and control signals are transferred among various kinds of units described above in both the MPU
1
and the HDC
2
.
FIGS. 2 and 3
are flow charts each showing the operation of the conventional system LSI shown in FIG.
1
.
The description will be given of the operation of the conventional system LSI.
First, a fetch operation of program codes performed by the CPU
3
in the MPU
1
for fetching program codes stored in one of the memories such as the ROM
13
and the SRAM
14
in the HDC
2
will be explained.
The CPU
3
outputs a branch request signal RCLR and a branch address AD_CPU to the CIU
4
when the address of the program is branched. When receiving the branch request signal RCLR and the branch address AD_CPU transferred from the CPU
3
, the CIU
4
outputs the branch address AD_CPU to the code address bus C_AD. In addition to this, the CIU
4
outputs a code read-out signal CRE to a bus (see FIG.
4
). When the branch address AD_CPU indicates a memory field in the ROM
13
in the HDC
2
, for example, the ROM
13
in the HDC
2
outputs a program code corresponding to the address to a code bus CB (See FIG.
4
).
Thereby, the CIU
4
may input the program code through the code bus CB, and outputs the program code to the ring buffer
5
. The ring buffer
5
stores the program code into an empty field indicated by a pointer of the ring buffer
5
. The CIU
4
then increments the pointer indicating the memory field in the ring buffer
5
, automatically, and continues the fetch operation to the ROM
13
unless the ring buffer
5
has an empty memory field in which no data item is stored. Hereinafter, the above operation will be referred to as a code pre-fetch operation.
In addition, when receiving the code request signal ROPC transferred from the CPU
3
, the CIU
4
outputs program codes stored in the ring buffer
5
to the CPU
3
through a bus OPC_BUS. The CIU
4
performs this operation independently from the pre-fetch operation. Hereinafter the above operation will be referred to as a code output operation. That is, when receiving the code request signal ROPC from the CPU
3
, the CIU
4
outputs program codes stored in the ring buffer
5
by the number of predetermined memory fields. This ring buffer
5
is a FIFO memory where a first inserted data item is output first.
When receiving the program codes from the CIU
4
, the CPU
3
decodes the program codes received, and then executes instructions obtained by this decoding operation.
Because the CIU
4
may perform the code pre-fetch operation and the code output operation in parallel, the CPU
3
gets the program-codes stored in the memories such as the ROM
13
, the SRAM
14
through the ring buffer
5
in the CIU
4
and may execute the instructions generated by the decoding operation for the program codes.
The description will be given of the data read operation by the HDC
2
from the memories such as the ROM
7
, the SRAM
8
, and the register
9
in the MPU
1
.
First, the HDC_CU
10
stores in the register
15
a
(Step ST
1
) addresses indicating data fields to be required (In this section, the address to be required indicate memory fields in the register
9
for easy explanation) and data informing that the memory access request signal transferred in the Step ST
2
(see
FIG. 2
) is a data read-out request signal for requesting a data read operation. In this case, it is possible for the CPU
3
to recognize the memory access request transferred from the HDC
2
by the following manner.
That is, the CPU
3
reads data stored in the register
15
a
at regular time intervals. When the data in the register
15
a
indicates the memory access request during the periodical data read operation, the CPU
3
recognizes the occurrence of the memory access request.
After Step ST
1
, because the HDC
2
can not directly access the memories such as the ROM
7
, the SRAM
8
, and the register
9
in the MPU
1
, the HDC
2
, that is, because the HDC
2
has no interface circuit for external memories such as the ROM
7
, the SRAM
8
, and the register
9
in the MPU
1
, the HDC_CU
10
in the HDC
2
generates and outputs the memory access request signal to the CPU
3
(see Step ST
2
).
When receiving the memory access request signal from the HDC_CU
10
, the CPU
3
outputs a data read request signal RDR to the DIU
6
, and further an address indicating the register
15
a
in the HDC
2
onto the bus AD_CPU, simultaneously. (In this case, it is determined in advance that the CPU
3
reads data stored in the register
15
a
when receiving the memory access request signal.)
When receiving the data read request signal RDR transferred from the CPU
3
and the address indicating the register
15
a
through the bus AD_CPU, the DIU
6
outputs this address to the data address bus D_AD and a data read-out signal DRE on a bus DRF (see FIG.
5
).
When receiving the data read-out signal DRE, the register
15
a
outputs the data stored therein to a data bus DB (see FIG.
5
). This data from the register
15
a
includes an address indicating the register
9
and information indicating that this memory access request signal is a data read-out request signal.
The DIU
6
gets the data through the data bus DB transferred from the register
15
a
temporarily (see
FIG. 5
) and then outputs the data to the CPU
3
through the bus D_BUS. Thereby, the CPU
3
obtains both the data read request from the HDC
3
and the address indicating a target data item to be read. When receiving this target address, the CPU
3
outputs both the data read request signal RDR to the DIU
6
through the bus and the target address indicating the register
9
in the MPU
1
through the bus AD_CPU, simultaneously.
When receiving the data read request signal RDR transferred from the CPU
3
and the target address indicating the register
9
through the bus AD_CPU, the DIU
6
o

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