Patent
1978-05-25
1981-02-03
Wojciechowicz, Edward J.
357 15, 357 34, 357 35, 357 44, 357 45, 357 46, 357 50, 357 51, 357 68, 357 71, 357 92, H01L 2702
Patent
active
042491932
ABSTRACT:
Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices.
In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.
REFERENCES:
patent: 3312871 (1967-04-01), Seki et al.
Balyoz John
Chang Chi S.
Fox Barry C.
Ghafghaichi Majid
Jen Teh-Sen
DeBruin Wesley
International Business Machines - Corporation
Wojciechowicz Edward J.
LandOfFree
LSI Semiconductor device and fabrication thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with LSI Semiconductor device and fabrication thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LSI Semiconductor device and fabrication thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-553282