Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-05
2001-11-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06321368
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to large scale integrated circuit (LSI) layout designing apparatuses, computer-implemented methods of designing LSI layout and computer readable storage mediums, and more particularly to a LSI layout designing apparatus and a computer-implemented method of designing LSI layout by computer aided design (CAD), and to a computer readable storage medium which stores a program for making a computer carry out a LSI layout design by such a LSI layout design method.
Recently, the number of elements in the LSIs has increased considerably, and the trend is for the functions of the LSIs to become more and more complex. In order to cope with the increasing elements and complexity of the LSIs, an electronic design automation (EDA) tool is essential when designing the LSIs.
Conventionally, the design process of the EDA is generally divided into a logic design process and a physical design process. A layout design process which designs the layout of the LSI is included in the physical design process.
A boundary between the logic design process and the physical design process originally is natural, and it is essentially unnecessary to integrate or feedback data between the logic design process and the physical design process, because the performance of the circuit is directly dependent upon a gate delay time. This gate delay time is the time required for a signal to propagate from an input terminal of the logic gate to an output terminal of the logic gate. In other words, the circuit performance is conventionally unaffected by a delay time generated in a wire which connects two logic gates.
For this reason, the person who designs the LSI designs the LSI using timing parameters which are based on characteristics of each of macro cells of the LSI. That is, the delay times of the connecting wires which are determined after determining the layout of the macro cells of the LSI have virtually no effect on the performance of the LSI. Accordingly, after making the logic design independently, the person who designs the LSI simply inputs the result of the logic design to an automatic LSI layout designing apparatus. The result of the logic design is often called a net list or logic circuit data.
However, the semiconductor production technology has developed considerably in recent years. As a result, the size of various elements have become extremely small, transistors having extremely high-speed switching capability have been developed, and the gate delay time has become extremely short. Consequently, the gate delay time is no longer the primary factor which determines the performance of the LSI, and instead, the delay times of the connecting wires have become dominant among the signal delay times. Hence, it is becoming more and more difficult to satisfy the timing specifications of the LSI when designing the LSI.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful LSI layout designing apparatus, computer-implemented method of designing LSI layout and computer readable storage medium, in which the problems described above are eliminated.
Another and more specific object of the present invention is to-provide a LSI layout designing apparatus, computer-implemented method of designing LSI layout and computer readable storage medium which are capable of quickly developing the LSI by taking into consideration elements of the logic design process in the layout design process which is included in the physical design process. According to the LSI layout designing apparatus, computer-implemented method of designing LSI layout and computer readable storage medium of the present invention, it is possible to eliminate the problems associated with the conventional layout design process which was unrelated to the logic design process. In other words, the present invention can quickly develop the LSI by reducing iterations between the logic design process and the layout design process, and by reducing the load of the layout design process itself.
Still another object of the present invention is to provide a LSI layout designing apparatus implemented by a computer and designing a layout of a LSI on a display screen, comprising timing adjusting means for carrying out a timing adjustment process with respect to logic circuit data of the LSI already subjected to a layout process, and layout restoration means for restoring an original layout of the LSI prior to the timing adjustment process and reflecting a change of cells caused by the timing adjustment process on the original layout which is displayed on the display screen. According to the LSI layout designing apparatus of the present invention, it is possible to prevent a timing error from being newly generated by the timing adjustment process, and to reduce the iterations between the logic design and the layout design (physical design), so as to enable quick developing of the LSI. Further, by re-using the original wirings to the extent possible, it is possible to eliminate the need to newly form all wirings to suit the layout which is modified according to the timing adjustment process. As a result, it is possible to prevent a new timing error from being generated by the wirings which are all newly formed, thereby enabling the layout design to be completed within a short time and realizing quick development of the LSI.
A further object of the present invention is to provide a computer-implemented method of designing a LSI layout on a display screen, comprising the steps of (a) carrying out a timing adjustment process with respect to logic circuit data of the LSI already subjected to a layout process, and (b) restoring an original layout of the LSI prior to the timing adjustment process and reflecting a change of cells caused by the timing adjustment process on the original layout which is displayed on the display screen. According to the computer-implemented method of the present invention, it is possible to prevent a timing error from being newly generated by the timing adjustment process, and to reduce the iterations between the logic design and the layout design (physical design), so as to enable quick developing of the LSI. Further, by re-using the original wirings to the extent possible, it is possible to eliminate the need to newly form all wirings to suit the layout which is modified according to the timing adjustment process. As a result, it is possible to prevent a new timing error from being generated by the wirings which are all newly formed, thereby enabling the layout design to be completed within a short time and realizing quick development of the LSI.
Another object of the present invention is to provide a computer readable storage medium which stores a program for causing a computer to design a LSI layout on a display screen, comprising timing adjusting means for causing the computer to carry out a timing adjustment process with respect to logic circuit data of the LSI already subjected to a layout process, and layout restoration means for causing the computer to restore an original layout of the LSI prior to the timing adjustment process and reflect a change of cells caused by the timing adjustment process on the original layout which is displayed on the display screen. According to the computer readable storage medium of the present invention, it is possible to prevent a timing error from being newly generated by the timing adjustment process, and to reduce the iterations between the logic design and the layout design (physical design), so as to enable quick developing of the LSI. Further, by re-using the original wirings to the extent possible, it is possible to eliminate the need to newly form all wirings to suit the layout which is modified according to the timing adjustment process. As a result, it is possible to prevent a new timing error from being generated by the wirings which are all newly formed, thereby enabling the layout design to be completed within a short time and realizing quick development of the LSI.
Arent Fox Kintner Plotkin & Kahn.
Do Thuan
Fujitsu Limited
Smith Matthew
LandOfFree
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