Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-26
2003-06-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06578179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an LSI layout design technique and particularly pertains to an LSI design apparatus, a layout design method using process migration, a recording medium recording a layout design program, and a semiconductor integrated circuit.
2. Description of the Related Art
As a mechanism for redesigning LSI layout data designed by an existing process technique by applying a new process technique, a design rule-based automatic layout generation tool by means of process migration has been widely adopted. If using this automatic layout generation tool, it is possible to generate layout data obtained by subjecting already designed circuit diagram information to shrink or the like according to a fine design rule based on a developed process technology.
FIG. 1A
shows an example of a circuit layout before process migration.
FIG. 2A
shows an example of a circuit layout after the process migration by which the circuit layout shown in
FIG. 1A
has been subjected to a shrinking processing by the above-stated generation tool. A shrink rate after the process migration is uniformly applied to a diffused layer
1
constituting the source/drain of a transistor, a gate electrode
2
and a metal wiring layer
3
constituting wirings. Also, the shape of the diagram and the relative positional relationship among the constituent elements are hardly changed before and after the process migration.
However, if attention is paid to the parasitic capacitances of the respective elements before and after the process migration, the shrink rate is not always applied to these parasitic capacitances uniformly.
FIG. 3
is a graph showing the capacitance changes of the diffused layer
1
constituting the source/drain of the transistor, the gate electrode
2
and the wirings
3
while the vertical axis of the graph indicates capacitance value and the horizontal axis thereof indicates shrink rate. If capacitance changes are observed from a point A (shrink rate=0) at which each capacitance value is an initial value, to a point B and to a point C in which order the shrink rate increases, the parasitic capacitances of the peripheral elements of the transistor, such as the diffused layer land the gate electrode
2
, tend to decrease and those of the wirings
3
hardly change or tend to slightly increase. Thus, the shrink rate does not influence the wirings
3
. This is because the two-dimensional areas of the wirings
3
are decreased by the shrinking processing by means of the process migration while the capacitance between the wirings is increased by shrinking a wiring distance.
FIG. 1B
is a cross-sectional view of the wiring layer taken along line
5
—
5
of FIG.
1
A.
FIG. 2B
is a cross-sectional view of the wiring layer taken along line
6
—
6
of FIG.
2
A. As can be seen from
FIGS. 1B and 2B
, the shrink rate by the process migration is applied to the two-dimensional direction of the wirings but hardly applied to the three-dimensional direction thereof. This is because the thickness of each wiring ((
3
) in
FIG. 2B
) cannot be made too small compared with the shrinkage of the wiring width ((
1
) and (
2
) in FIG.
1
B).
Furthermore, as fine machining has been developed recently, the cross-sectional structure of a wiring tends to have a higher aspect ratio and the capacitance between wirings tends to increase.
As stated above, if attention is paid to the parasitic capacitances of the constituent elements before and after the process migration, it is seen that the relationship of the parasitic capacitances in the layout design before the process migration is not shrunk under uniform conditions. As a result, the capacitances are unbalanced on the layout after the process migration compared with the layout before the process migration.
If a size for determining the driving force of a transistor driving each node is uniformly shrunken in this state, then the balance between the driving force and the load of the transistor is destroyed by unbalanced capacitances, the relationship of operation timing which has been optimized in the capacitance distribution before the process migration is disturbed accordingly, and such problems as decreased operating speed and malfunction may possibly occur.
SUMMARY OF THE INVENTION
An LSI layout design apparatus in one embodiment according to the present invention includes: a process migration section conducting process migration for converting first layout data according to a first design standard into second layout data according to a second design standard and a designated transistor size; an extraction section extracting transistor sizes and parasitic capacitances from the first layout data and the second layout data, respectively, for each node; a delay time calculation section calculating first delay time from the transistor size and the parasitic capacitance extracted from the first layout data and a driving current value of a transistor based on the first design standard, and calculating second delay time from the transistor size and the parasitic capacitance extracted from the second layout data and a driving current value of the transistor based on the second design standard; and an optimum value calculation section calculating an optimum value of the transistor size after the process migration in order that the second delay time becomes equal to the first delay time.
In addition, according to an LSI layout design method in one embodiment according to the present invention includes: conducting process migration for designating a transistor size, and converting first layout data according to a first design standard into second layout data according to a second design standard; extracting a transistor size and a parasitic capacitance for each node from said first layout data; calculating first delay time from the transistor size and the parasitic capacitance extracted from said first layout data and a driving force of a transistor based on said first design standard; extracting a transistor size and a parasitic capacitance for each node from said second layout data; calculating second delay time from the transistor size and the parasitic capacitance extracted from said second layout data and a driving force of the transistor based on said second design standard; calculating an optimum value of the transistor size after the process migration in order that said second delay time becomes equal to said first delay time; comparing the transistor size extracted from said second layout data with said optimum value, and obtaining a differential value; and executing said process migration again based on the calculated optimum value of the transistor size if said differential value obtained as a result of comparison is out of a predetermined range.
Further, an LSI layout design program stored in a computer readable recording medium in one embodiment according to the present invention includes: conducting process migration for designating a transistor size, and converting first layout data according to a first design standard into second layout data according to a second design standard; extracting a transistor size and a parasitic capacitance for each node from said first layout data; calculating first delay time from the transistor size and the parasitic capacitance extracted from said first layout data and a driving force of a transistor based on said first design standard; extracting a transistor size and a parasitic capacitance for each node from said second layout data; calculating second delay time from the transistor size and the parasitic capacitance extracted from said second layout data and a driving force of the transistor based on said second design standard; calculating an optimum value of the transistor size after the process migration in order that said second delay time becomes equal to said first delay time; comparing the transistor size extracted from said second layout data with said optimum value, and obtaining a differential value; and executing said process migration again
Shirotori Tsukasa
Urakawa Yukihiro
Kabushiki Kaisha Toshiba
Lin Sun James
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Siek Vuthe
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