Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-23
2002-07-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06415423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improvement of an LSI design system using a computer, and more particularly to an LSI design system which is capable of preventing the occurrence of voltage drop and noise which are caused by the concentration of cells or wirings.
2. Description of the Related Arts
Recently, along with the advancement of the fine processing technology, the high integration of the LSI has been progressed and hence, the demand for further speedup or further lowering of voltages of an LSI and the demand for the development of an LSI in a short period are increasing.
In designing the densely packed cells and wirings, voltage drop and noise occur due to the partial concentration of consumed power and this causes the malfunction of the LSI and lowering of the yield. This is caused by a following reason. That is, the voltage drop occurs in case the consumed power of the cells connected to power trunks is relatively large compared to the power supplied to the power trunks. When the voltage drop occurs, there arises a problem that driving of cells connected to the power trunks requires a long time or cells become inoperable. On the other hand, noise occurs in the following manner. That is, when signals are changed approximately in the identical timing at a plurality of neighboring wirings, a capacitance constructed between wires mediates unexpected signal as noise. This noise causes the delay or rashness of the signal.
As illustrated in
FIG. 23
, when a plurality of cells having a large consumed power, for example, cells which are given instance names A-D are arranged in such a manner that they are concentrated at one place, voltage drop occurs thus giving rise to a malfunction of a circuit.
Conventionally, the layout of wirings has been designed in such a manner that the wirings are arranged without taking change of signals into account. With respect to three wirings N
1
, N
2
, N
3
illustrated in
FIG. 24
which generate change of signals, when two wirings N
1
, N
2
which generate change of signals in the identical timing are arranged close to each other as shown in
FIG. 25
, noise occurs thus giving rise to a malfunction of the circuit.
Conventionally, based on information on an arrangement of cells and wirings obtained after designing the layout, in case voltage drop is greater than the minimum operating voltage, the cells which are subjected to such a voltage drop are rearranged so as to ensure the minimum operating voltage thus preventing the voltage drop. One example of such method has been disclosed in Japanese laid-open patent publication Hei 9-130622, the U.S. Pat. No. 5,598,348 and the U.S. Pat. No. 5,751,957.
Furthermore, considering the necessity of preventing the occurrence of noise, with respect to wirings which are arranged in parallel to each other, it has been recommended to set a wide spacing between wirings from the beginning.
The rearrangement of cells after completion of the designing of the layout requires considerable efforts and time. Furthermore, in case the rearrangement of cells turns out to be insufficient to prevent voltage drop, the layout of the entire circuit must be designed again. Such a redesigning of the layout prolongs the development period of the LSI.
Setting of the wide spacing or distance between wirings from the beginning to obviate such troubles, on the other hand, increases the area of the LSI, gives rise to an increase of cost and makes the high integration of the LSI difficult.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an LSI design system which can prevent voltage drop without necessitating rearranging of cells after designing of a layout, redesigning of an entire circuit, or setting of a wide spacing between wirings.
It is another object of the present invention to provide an LSI design system which can prevent the occurrence of noise without necessitating rearranging of cells after designing of a layout, redesigning of an entire circuit, or setting of a wide spacing between wirings.
To achieve the above objects, the LSI design system of the present invention is constructed by including separation information generating means which generates information on cells to be separated which require a separate arrangement from each other based on the relative comparison of respective consumed powers of cells which are subjected to a layout, and layout generating means which generates a layout based on the information.
The cells to be separated which have to be arranged in a spaced-apart manner are arranged in a spaced-apart manner from the beginning of an layout based on the information of the separation information generating means.
REFERENCES:
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5751597 (1998-05-01), Okano et al.
patent: 5878053 (1999-03-01), Koh et al.
patent: 5933358 (1999-08-01), Koh et al.
patent: 5943487 (1999-08-01), Messerman et al.
patent: 10-21289 (1998-01-01), None
patent: 10-321729 (1998-12-01), None
Takahashi Miwaka
Toyonaga Masahiko
Dinh Paul
Jacobson & Holman PLLC
Matsushita Electric - Industrial Co., Ltd.
Smith Matthew
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