LSI design method

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000

Reexamination Certificate

active

11014814

ABSTRACT:
An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.

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patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6594805 (2003-07-01), Tetelbaum et al.
patent: 6647540 (2003-11-01), Lindkvist et al.
patent: 7096442 (2006-08-01), Lu et al.
patent: 2005/0081171 (2005-04-01), Kawano et al.
patent: 2005/0107970 (2005-05-01), Franch et al.
patent: 2005/0138588 (2005-06-01), Frenkil
patent: 2001-196459 (2001-07-01), None

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