Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-19
2009-06-23
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07552411
ABSTRACT:
In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an input pattern causing the extracted pair to perform concurrent transition. When an input pattern causing concurrent transition is found, the searching unit determines the extracted pair to be a pair capable of concurrent transition (concurrent transition pair), and holds the input pattern causing concurrent transition. When an input pattern causing concurrent transition is not found, the searching unit determines the extracted pair to be a non-concurrent transition pair. An input pattern operation ratio calculating unit calculates an input pattern operation ratio for each input pattern causing concurrent transition. A detecting unit detects an input pattern yielding the highest input pattern operation ratio. An output unit puts out the detected input pattern, non-concurrent transition pairs, etc.
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Gregory Steele et al, “Full Chip Verification Methods for DSM Power Distribution Systems” 35th Design Automation Conference, Jun. 1998.
Harish Kriplani et al., “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlation, and Their Resolution” IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems vol. 14 No. 8, Aug. 1995, (pp. 998-1012).
Angela Krstic et al., “Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits” Design Automation Conference, 1997.
Dimyan Magid Y
Fujitsu Limited
Staas & Halsey , LLP
Whitmore Stacy A
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