Lower power high speed design in BiCMOS processes

Details Lower power high speed design in BiCMOS processes Lower power high speed design in BiCMOS processes

2006-10-24

2006-10-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

C326S109000, C326S115000

Reexamination Certificate

active

07126382

ABSTRACT:
A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.

REFERENCES:
patent: 5283479 (1994-02-01), Rosseel et al.
patent: 5298810 (1994-03-01), Scott et al.
patent: 5304869 (1994-04-01), Greason
patent: 5420529 (1995-05-01), Guay et al.
patent: 5990718 (1999-11-01), Tchamov et al.
patent: 6433595 (2002-08-01), Tung et al.
Paul R. Gray et al., “Single-Transistor and Multiple-Transistor Amplifiers, Multiple-Transistor Amplifier Stages,” Analysis and Design of Analog Integrated Circuits, Fourth Edition, pp. 206-211.
Michael M. Green et al., “Design of CMOS CML Circuits for High-Speed Broadband Communications,” IEEE 2003, pp. II-204-II-207.
H.-M. Rein et al., “Design Considerations for Very-High-Speed Si-Bipolar IC's Operating up to 50 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 1996, pp. 1076-1090.

Affiliated with

Also associated with

Rating

Lower power high speed design in BiCMOS processes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Lower power high speed design in BiCMOS processes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lower power high speed design in BiCMOS processes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3695677