Lower-jitter phase-locked loop

Details Lower-jitter phase-locked loop Lower-jitter phase-locked loop

2000-01-05

2004-04-27

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S175000, C700S280000

Reexamination Certificate

active

06728327

ABSTRACT:

BACKGROUND
Electronic systems such as digital clocks or circuits for synthesizing analog frequencies typically require a clock signal having a lower jitter in its output. Clock jitter refers to fluctuation in the phase of a signal and also encompasses phase noise. A crystal reference may be utilized to provide a lower jitter, however crystals are relatively expensive and difficult to integrate with an integrated circuit. A phase-locked loop (PLL) may be utilized to generate a clock signal, however the output of a phase-locked loop generally have an unacceptable amount of jitter for certain applications. Jitter in a PLL may be reduced by designing the PLL with a higher precision loop filter, a higher precision phase comparator, or a higher-order feedback network. However, these techniques for reducing PLL jitter are disadvantageous in that a larger area on an integrated circuit is required, and lock-in time, circuit complexity, and noise sensitivity are increased.


REFERENCES:
patent: 4970474 (1990-11-01), Kennedy et al.
patent: 5710720 (1998-01-01), Algrain et al.
patent: 6356129 (2002-03-01), O'Brien et al.
patent: 6469550 (2002-10-01), Kurd

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