Low-voltage trigger electrostatic discharge protection circuit

Details Low-voltage trigger electrostatic discharge protection circuit Low-voltage trigger electrostatic discharge protection circuit

1996-11-25

1998-04-21

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257356, 257146, 257162, 257173, 257124, H01L 2362

Patent

active

057420858

ABSTRACT:
A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 .mu.m.sup.2 smaller than that of prior art for space saving. For more precise statement, the invention provides about 10% chip area saving.

REFERENCES:
patent: 4400711 (1983-08-01), Avery
patent: 5077591 (1991-12-01), Chen et al.
patent: 5576557 (1996-11-01), Ker et al.
patent: 5682047 (1997-10-01), Consiglio et al.

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