Low voltage trigger and save area electrostatic discharge...

Details Low voltage trigger and save area electrostatic discharge... Low voltage trigger and save area electrostatic discharge...

2007-09-04

2007-09-04

Tsai, H. Jey (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S356000, C257SE29331

Reexamination Certificate

active

11215492

ABSTRACT:
Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.

REFERENCES:
patent: 2005/0275065 (2005-12-01), Cogan et al.

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