Low voltage test mode operation enable scheme with hardware safe

Static information storage and retrieval – Read/write circuit – Testing

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Details

36518905, 36518908, 36518509, 371 211, G11C 700

Patent

active

058257004

ABSTRACT:
A test mode circuit for use in a data system includes a test mode code latch for receiving a test mode code. A switch, which when turned on, couples the test mode code latch to the input so that the test mode code can be transferred from the input to the test mode code latch. A test mode command decoder is coupled to the test mode code latch for decoding the test mode code to initiate a test mode of operation in the data system. A data storage unit is coupled to the test mode command decoder for storing a data bit which corresponds to a low voltage test mode enable signal. The data bit may be modified during the test mode of operation. A low voltage test mode circuit is coupled to the data storage unit which, after first being enabled by the low voltage test mode enable signal, can be controlled to turn the switch on and off. An enable signal generation circuit couples the low voltage test mode circuit to the switch for turning the switch on and off. A method of loading a test mode code into a data system is also disclosed.

REFERENCES:
patent: 4309627 (1982-01-01), Tabata
patent: 4321489 (1982-03-01), Higuchi et al.
patent: 4437025 (1984-03-01), Liu et al.
patent: 4571704 (1986-02-01), Bohac, Jr.
patent: 4658156 (1987-04-01), Hashimoto
patent: 4858185 (1989-08-01), Kowshik et al.
patent: 4922133 (1990-05-01), Iwahashi et al.
patent: 5031142 (1991-07-01), Castro
patent: 5047664 (1991-09-01), Moyal
patent: 5077738 (1991-12-01), Larsen et al.
patent: 5083045 (1992-01-01), Yim et al.
patent: 5097146 (1992-03-01), Kowalski et al.
patent: 5118968 (1992-06-01), Douglas et al.
patent: 5134586 (1992-07-01), Steele
patent: 5144159 (1992-09-01), Frisch et al.
patent: 5177745 (1993-01-01), Rozman
patent: 5214316 (1993-05-01), Nagai
patent: 5262990 (1993-11-01), Mills et al.
patent: 5278458 (1994-01-01), Holland et al.
patent: 5280198 (1994-01-01), Almulla
patent: 5293610 (1994-03-01), Schwarz
patent: 5311470 (1994-05-01), Atsumi et al.
patent: 5317532 (1994-05-01), Ochii
patent: 5378936 (1995-01-01), Kokubo et al.
patent: 5408435 (1995-04-01), McClure et al.
patent: 5469100 (1995-11-01), Wuidart et al.
patent: 5526364 (1996-06-01), Roohparvar
patent: 5615159 (1997-03-01), Roohparvar
patent: 5627784 (1997-05-01), Roohparvar
patent: 5636166 (1997-06-01), Roohparvar
patent: 5677885 (1997-10-01), Roohparvar
U.S. Ser. No. 08/386,704 filed Feb. 10, 1995, Roohparvar.
U.S. Ser. No. 08/493,162 filed Jun. 21, 1995, Roohparvar.
U.S. Ser. No. 08/508,864 filed Jul. 28, 1995, Roohparvar et al.
U.S. Ser. No. 08/508,828 filed Jul. 28, 1995, Roohparvar et al.

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