Low-voltage single-layer polysilicon EEPROM memory cell

Details Low-voltage single-layer polysilicon EEPROM memory cell Low-voltage single-layer polysilicon EEPROM memory cell

2006-10-11

2008-08-05

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

07408812

ABSTRACT:
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

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U.S. Appl. No. 11/548,512 (incl. drawings), “Low-Voltage Single-Layer Polysilicon EEPROM Memory Cell”, filed Oct. 11, 2006, Assignee: Atmel Corporation, Inventor: Muhammad I. Chaudhry et al.

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