Low voltage RAM cell

Static information storage and retrieval – Read/write circuit – Data refresh

Patent

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Details

365149, 357 23, G11C 1140

Patent

active

044919387

ABSTRACT:
A memory cell includes a gated capacitor connected to a first node and also connected to a refresh line. The memory cell further includes a transistor that is also connected to the first node and to a second node with the gate terminal being connected to a second refresh line. The second node is connected to the bit line used to access the bit information contained in the cell. A second transistor is included that has one side connected to a power line, the second side connected to the second node and the gate terminal connected to the first node. A first refresh signal is provided on the refresh line connected to the gated capacitor and a second refresh signal is provided to the gate of the first transistor. The second refresh signal is of a voltage magnitude greater than the voltage provided on the power line and the second refresh signal is also provided at a time during which the first refresh signal is absent. Also provided is a semiconductor capacitor that includes the region of a first plurality located in a semiconductor substrate of opposite plurality with a layer of silicon dioxide located on top of the region and on an area adjacent to this region. A metal layer is located on top of the silicon dioxide layer and adjacent to a gap which is made up of the first plurality type and located in the semiconductor substrate and adjacent to the region of first plurality together with being adjacent to the metal layer.

REFERENCES:
patent: 4291393 (1981-09-01), Wilson

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