Low voltage planar power MOSFET with serpentine gate pattern

Details Low voltage planar power MOSFET with serpentine gate pattern Low voltage planar power MOSFET with serpentine gate pattern

2000-03-28

2003-04-01

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S342000, C257S343000, C257S344000, C257S355000, C257S365000

Reexamination Certificate

active

06541820

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to MOSgated semiconductor devices, and more specifically relates to a novel process and resulting article for a low voltage very low V
ON
device made with minimum number of masks.
BACKGROUND OF THE INVENTION
MOSgated devices such as power MOSFETs are well known. The manufacturing process for such devices usually requires a large number of masks and long oxidation and drive steps. Further, such devices usually are vertical conduction devices, requiring a backside metallization and the use of expensive silicon wafers with epitaxial junction-receiving layers.
It would be very desirable to produce a low cost MOSgated device with a simpler process in non-epi, float zone material with a very low V
ON
.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, a novel process and device are formed, using a laterally interdigitated topology, and using as few as 3 masks in the process.
Thus, the surface of a silicon wafer, in which a plural identical die are formed is first oxidized to form a gate oxide layer and is then covered with a conductive polysilicon gate. A serpentine gate pattern, with reentrant segments, is then defined in a first mask step wherein the areas on opposite sides of the serpentine gate are to become respective and identical source and drain areas.
A light phosphorus dose is then implanted to ultimately define a lightly doped source/drain region. A Lightly Doped Drain (LDD) structure is known to increase drain breakdown voltage and therefore device operational voltage. An LTO (low temperature oxide) layer is then formed and then plasma etched, leaving a side wall spacer about and along the edge of the polysilicon gate. A heavy arsenic implant is next applied to the source/drain areas through this new and narrowed window.
A titanium layer is then deposited atop the wafer surface and is alloyed to form a silicide with the exposed silicon and is etched. Thereafter a low temperature oxide or nitride is deposited atop the wafer. A second mask, which is non-critically aligned with the first is a contact mask to permit selective and spaced gate, drain and source contacts to the wafer/die surface. (Note that the terms “source” and “drain” are interchangeable.)
Thereafter, aluminum is sputtered atop the wafer surface, making contact through the windows in the LTO to the source, drain and gate regions. A non critical aligned contact mask operation is then used to separate the metal contacts to the various electrodes. Selective electroplating can be employed at this step to further increase metal thickness.
The final device will have a very low R
DSON
(or V
ON
). The process is very simple, requiring only 3 masks and no long oxidation or drive steps. No backside metallization is needed and no epi is required. The wafers are also easy to modularize. It has been found that a finished 5 inch wafer can be produced at a total cost of under about $60.


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