Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1996-01-11
1998-06-16
Westin, Edward P.
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 81, 326 83, 326 27, H03K 190175, H03K 19094
Patent
active
057676976
ABSTRACT:
A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off. The circuit further includes a device for restricting current flow from the output terminal to the predetermined potential side through the first and second transistors.
REFERENCES:
IBM Technical Disclosure Bulletin, vol. 34, No. 4B, pp. 147-149, Sep. 1, 1991, "Mixed Technology Overvoltage Protection".
Noine Yasukazu
Ueno Masaji
Kabushiki Kaisha Toshiba
Roseen Richard
Westin Edward P.
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