Low voltage output buffer with improved speed

Details Low voltage output buffer with improved speed Low voltage output buffer with improved speed

1994-07-28

1995-05-23

Hudspeth, David R.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 81, 327374, 327437, H03K 1716, H03K 19003

Patent

active

054184762

ABSTRACT:
An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

REFERENCES:
patent: 4704547 (1987-11-01), Kirsch
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5239211 (1993-08-01), Jinbo
patent: 5289025 (1994-02-01), Lee
patent: 5343099 (1994-08-01), Shichinohe
IEEE 1992 Custom Integrated Circuits Conference. "3.3V-5V Compatible I/O Circuit Without Thick Gate Oxide". Makoto Takahashi et al. 23.3.1-23.3.4.
Patent application Ser. No. 08/144,594, filed Oct. 28, 1993, titled "Multi-Voltage Compatible Bidirectional Buffer" by Bernard Lee Morris.

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