Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2007-06-27
2010-11-23
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S230060
Reexamination Certificate
active
07839701
ABSTRACT:
Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drain transistors coupled to the sense or restore signals and driven by gate voltages which extend outside of the voltage range between VSSand VDD. The drain transistors are self reverse-biased in a standby mode. A method is also described for reducing leaking in non-complementary sense amplifiers by modifying the sense and restore gate voltages. Another aspect is a new negative word line method utilizing stacked pull-down transistors and a multi-step control circuit. In addition a level shifter scheme is described for preventing unwanted current flow between voltage sources while discharging control signal PX.
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O'Banion John P.
Tran Michael T
ZMOS Technology, Inc.
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