Low-voltage non-volatile semiconductor memory device

Details Low-voltage non-volatile semiconductor memory device Low-voltage non-volatile semiconductor memory device

2005-05-03

2005-05-03

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185230

Reexamination Certificate

active

06888756

ABSTRACT:
The disclosure is a non-volatile semiconductor memory device including a bias circuit that generates a bias voltage for controlling an NMOS transistor connected to both a bit line and a page buffer circuit. The bias circuit generates a first voltage, which is greater than a power source voltage, as the bias signal in a precharge period of a read operation. The bias circuit also generates a second voltage, which is less than the power source voltage, as the bias signal in a sensing period of the read operation.

REFERENCES:
patent: 5677873 (1997-10-01), Choi et al.
patent: 5715194 (1998-02-01), Hu
patent: 5949727 (1999-09-01), Choi et al.
patent: 5991202 (1999-11-01), Derhacobian et al.
patent: 6049493 (2000-04-01), Kitamoto et al.
patent: 6061270 (2000-05-01), Choi
patent: 6064611 (2000-05-01), Tanaka et al.
patent: 6212120 (2001-04-01), Nakamura et al.
patent: 6330178 (2001-12-01), Sakata et al.

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