Low voltage non-volatile memory transistor

Details Low voltage non-volatile memory transistor Low voltage non-volatile memory transistor

2006-08-15

2006-08-15

Smith, Bradley K. (Department: 2891)

Static information storage and retrieval

Read only systems

Semiconductive

C438S132000, C438S281000, C438S467000, C257S413000, C257S529000, C257S757000, C257S904000, C365S096000, C365S177000, C365S184000

Reexamination Certificate

active

07092273

ABSTRACT:
A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

REFERENCES:
patent: 4219836 (1980-08-01), McElroy
patent: 4238839 (1980-12-01), Redfern et al.
patent: 4647340 (1987-03-01), Szluk et al.
patent: 4872140 (1989-10-01), Graham et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6258700 (2001-07-01), Bohr et al.
patent: 6496416 (2002-12-01), Look
patent: 6525397 (2003-02-01), Kalnitsky et al.
patent: 6671205 (2003-12-01), Look
patent: 6703680 (2004-03-01), Toyoshima
patent: 6807079 (2004-10-01), Mei et al.
patent: 6882571 (2005-04-01), Look
patent: 6911360 (2005-06-01), Li et al.
patent: 6930920 (2005-08-01), Look
patent: 6936527 (2005-08-01), Look
patent: 2003/0122200 (2003-07-01), Kamiya et al.
patent: 2004/0124458 (2004-07-01), Kothandaraman
patent: 2005/0067670 (2005-03-01), Hui
Toyoji Yamamoto et al., “Bias Temperature Instability in Scaled p+ Polysilicon Gate p-MOSFET's,” IEEE Transactions on Electron Devices, vol. 46, No. 5, May 1999, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
N. Kimizuka et al., “NBTI enchancement by nitrogen incorporation into ultrathin gat oxide for 0.10-um gate CMOS generation,” 200 Symposium on VLSI Technology Digest of Technical Papers, Apr. 2000, pp. 92-93, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jerome B. Lasky et al., “Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi and CoSi2,” IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 262-269, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Se-Augjang et al., “Effects of Thermal Processes After Silicidation on the Performance of TiSi2/Polysilicon Gate Device,” IEEE Transactions on Electron Devices, vol. 46, No. 12, Dec. 1999, pp. 2353-2356, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Mohsen Alavi et al., A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process, Jul. 1997, pp. 855-858, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Alexander Kalnitzky et al., CoSi2integrated fuses on poly silicon for low voltage 0.18um CMOS applications, Sep. 1999, pp. 765-768 IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.

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