Low-voltage non-degenerative transmitter circuit

Details Low-voltage non-degenerative transmitter circuit Low-voltage non-degenerative transmitter circuit

2005-01-11

2005-01-11

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000, C326S062000, C326S068000, C326S081000, C326S083000

Reexamination Certificate

active

06842041

ABSTRACT:
A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

REFERENCES:
patent: 5889701 (1999-03-01), Kang et al.
patent: 5995010 (1999-11-01), Blake et al.
patent: 6114843 (2000-09-01), Olah
patent: 6288526 (2001-09-01), Olah
patent: 6344758 (2002-02-01), Turner et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6470466 (2002-10-01), Takahashi
patent: 6590416 (2003-07-01), Davies et al.
Xilinx Advance Product Specification DS012 (v1.4) “Cool Runner XPLA3 CPLD” Apr. 11, 2001, pp. 1-10.

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