Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-08
2002-02-12
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S365000, C257S408000, C257S343000
Reexamination Certificate
active
06346726
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to MOSgated power devices and more specifically relates to a novel MOSgated device having a minimum figure of merit, a novel process for its manufacture, and a novel circuit application of the device.
Low voltage power MOSgated devices, particularly power MOSFETs, are well known and are commonly made with planar or trench topologies. The trench topologies have been used for very low voltage devices which are to have the lowest possible switching losses in high frequency applications such as in d-c to d-c converters used for producing a regulated d-c voltage for portable electronic devices powered from a battery. By reducing switching loss, battery life can be extended for such portables as lap top computers.
Switching loss is determined, in part, by the figure of merit of the MOSFET, which is the product of its on-resistance R
DSON
and its gate charge Q
g
. A minimum figure of merit is desired for high frequency, low voltage MOSFETs. Trench devices have been useful in these applications because it was believed that they had an inherently lower Q
g
than that of planar designs.
Planar technology MOSFETs using spaced closed polygonal cells are well known, and are shown, for example, in U.S. Pat. No. 5,008,725, and in
FIG. 12
herein. These devices have a relative lower on-resistance R
DSON
than equivalent trench designs, but, because of the geometry of the polygonal design (usually hexagonal or rectangular base cells) the polysilicon gate extends across areas such as areas
30
, shown in
FIG. 12
for a hexagonal cell topology, which do not contribute to invertible channel width. More specifically,
FIG. 12
shows polysilicon web
31
containing windows
32
,
33
,
34
and
35
used to define diffused bases or channels, shown in dotted lines. The window openings such as opening
36
was conventionally 5.8 microns in low voltage designs. The polysilicon
31
overlies areas
30
, which are inactive, contribute heavily to the polysilicon gate to-drain capacitance, and thus to Q
g
.
Planar designs have also used a stripe topology, using elongated, spaced base stripes. While these designs have a lower Q
GD
than cellular designs, they usually have an increased on-resistance, and the figure of merit was not believed to be reduced by the planar stripe design.
It would be desirable to use a planar stripe topology for a low voltage power MOSgated device in which the figure of merit, that is, the product of Q
G
and R
DSON
can be reduced.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, it has been found that a topology, employing parallel base stripes with a polysilicon line spacing between less than about 1.5 microns to about 2.5 microns, with a polysilicon line width of about 2.6 to about 8.0 microns, depending on the drain to source voltage rating. For a 30 volt device, it would be from 3.2 to 3.5 microns, preferably 3.4 microns. A base to base spacing of about 0.8 microns or greater will produce a minimum figure of merit. It has been found that the increased channel width per unit area produced by the closer spacing of the polysilicon lines reduces R
DSON
proportionally more than Q
g
increases, with a practical minimum figure of merit being reached at a polyline spacing of about 1.5 microns. The figure of merit obtained with this novel geometry is lower than that obtained with equivalent die areas employing either trench technology or closed polygonal cell technology.
Further, the present invention produces a device having both an extremely low R
DSON
and an extremely high avalanche energy.
Another feature of the invention employs the polysilicon stripes to define a mask for the formation of three sequential regions, the first being a base (or channel) diffusion, the second being a source diffusion and the third being a higher concentration base region which underlies the first base and which does not invade the invertible channel formed by the first base and source. The third region is formed by an implant through the polysilicon window and a subsequent anneal.
A novel application of the invention is for d-c to d-c converter circuits using a control MOSFET and a synchronous rectifier MOSFET. Both of these MOSFETs are made by the process of the invention and differ only in die area.
REFERENCES:
patent: 5541429 (1996-07-01), Shibib
patent: 5616945 (1997-04-01), Williams
patent: 5703389 (1997-12-01), Knoch
patent: 5795793 (1998-08-01), Kinzer
patent: 5960275 (1999-09-01), So et al.
patent: 5990518 (1999-11-01), Kobayashi et al.
patent: 6031702 (2000-02-01), Williams
patent: 6049104 (2000-04-01), Hshieh et al.
Femy Jesse A.
International Rectifier Corp.
Lee Eddie
LandOfFree
Low voltage MOSFET power device having a minimum figure of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low voltage MOSFET power device having a minimum figure of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage MOSFET power device having a minimum figure of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2984376