Low voltage low power n-channel flash memory cell using gate ind

Details Low voltage low power n-channel flash memory cell using gate ind Low voltage low power n-channel flash memory cell using gate ind

1998-10-22

2000-08-29

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257316, H01L 2976, H01L 29788

Patent

active

061112860

ABSTRACT:
A flash memory cell formed on a semiconductor substrate is disclosed. The cell comprises: a p-well formed in the substrate; a gate structure formed atop the p-well, the gate structure including a control gate and a floating gate, the floating gate electrically isolated from the control gate and the semiconductor substrate by a thin dielectric layer; an n- base formed adjacent to a first edge of the gate structure and extending underneath the gate structure; a p+ structure formed within the n- base and adjacent to the first edge of the gate structure; and a n+ structure adjacent a second edge of the gate structure. With such a structure, it is possible to program the cell by band-to-band tunneling enhanced hot electrons generated at the p+ surface. The erase is performed by Fowler-Nordheim tunneling through the n- base region.

REFERENCES:
patent: 5350938 (1994-09-01), Matsukawa et al.
patent: 5770963 (1998-06-01), Akaogi et al.
patent: 5956271 (1999-09-01), Kaya
patent: 6043123 (2000-03-01), Wang et al.

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