Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1997-01-15
1999-08-03
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 83, H03K 190185
Patent
active
059330252
ABSTRACT:
A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.
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Bazargan Hassan K.
Li Richard C.
Nance Scott S.
Tamjidi Mohammad R.
Wong Jennifer
Hoffman E. Eric
Le Don Phu
Santamauro Jon
Xilinx , Inc.
Young Edel M.
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