Low voltage interface circuit

Electronic digital logic circuitry – Interface

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S063000, C326S081000, C327S333000, C327S057000

Reexamination Certificate

active

07956641

ABSTRACT:
An improved interface circuit is provided herein for translating a relatively high input voltage into a relatively low output voltage using only low voltage transistors and a single, low voltage power supply. According to one embodiment, the interface circuit includes a power supply, a pair of input transistors with source terminals coupled together for receiving a relatively low voltage from the power supply, and a current sense amplifier with a pair of input terminals, each coupled to a drain terminal of a different one of the pair of input transistors for receiving a pair of differential currents and for generating a pair of differential voltages therefrom.

REFERENCES:
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4150308 (1979-04-01), Adlhoch
patent: 4178558 (1979-12-01), Nagashima et al.
patent: 4264872 (1981-04-01), Suzuki
patent: 4288804 (1981-09-01), Kikuchi et al.
patent: 4397003 (1983-08-01), Wilson et al.
patent: 4475050 (1984-10-01), Noufer
patent: 4669063 (1987-05-01), Kirsch
patent: 4771194 (1988-09-01), Zeghbroeck
patent: 4943738 (1990-07-01), Hoshi
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 4973864 (1990-11-01), Nogami
patent: 4978870 (1990-12-01), Chen et al.
patent: 5029137 (1991-07-01), Hoshi
patent: 5113097 (1992-05-01), Lee
patent: 5130581 (1992-07-01), Oh et al.
patent: 5148399 (1992-09-01), Cho et al.
patent: 5175450 (1992-12-01), Chern
patent: 5300832 (1994-04-01), Rogers
patent: 5327379 (1994-07-01), Pascucci
patent: 5349305 (1994-09-01), Hsiao et al.
patent: 5396467 (1995-03-01), Liu et al.
patent: 5412348 (1995-05-01), Kasha et al.
patent: 5440162 (1995-08-01), Worley et al.
patent: 5477497 (1995-12-01), Park et al.
patent: 5539334 (1996-07-01), Clapp et al.
patent: 5650971 (1997-07-01), Longway et al.
patent: 5698993 (1997-12-01), Chow
patent: 5701268 (1997-12-01), Lee et al.
patent: 5732015 (1998-03-01), Kazerounian et al.
patent: 5737260 (1998-04-01), Takata et al.
patent: 5742183 (1998-04-01), Kuroda
patent: 5744982 (1998-04-01), Chu
patent: 5821800 (1998-10-01), Le et al.
patent: 5850365 (1998-12-01), Reese et al.
patent: 5892371 (1999-04-01), Maley
patent: 5942921 (1999-08-01), Talaga, Jr.
patent: 6023174 (2000-02-01), Kirsch
patent: 6052324 (2000-04-01), Tobita
patent: 6061267 (2000-05-01), Houston
patent: 6067256 (2000-05-01), Yamashita et al.
patent: 6069515 (2000-05-01), Singh
patent: 6115309 (2000-09-01), Coleman, Jr.
patent: 6137319 (2000-10-01), Krishnamurthy et al.
patent: 6147540 (2000-11-01), Coddington
patent: 6184738 (2001-02-01), Iwamoto et al.
patent: 6240027 (2001-05-01), Lee et al.
patent: 6271707 (2001-08-01), Le et al.
patent: 6275070 (2001-08-01), Pantelakis et al.
patent: 6292025 (2001-09-01), Okumura
patent: 6314028 (2001-11-01), Kono
patent: 6331791 (2001-12-01), Huang
patent: 6370072 (2002-04-01), Dennard et al.
patent: 6396310 (2002-05-01), Shin
patent: 6400189 (2002-06-01), McDaniel
patent: 6411559 (2002-06-01), Yokozeki
patent: 6411560 (2002-06-01), Tanizaki et al.
patent: 6414534 (2002-07-01), Wang et al.
patent: 6430095 (2002-08-01), Casper
patent: 6449202 (2002-09-01), Akatsu et al.
patent: 6480037 (2002-11-01), Song et al.
patent: 6483349 (2002-11-01), Sakata et al.
patent: 6483386 (2002-11-01), Cress et al.
patent: 6501306 (2002-12-01), Kim et al.
patent: 6501696 (2002-12-01), Mnich et al.
patent: 6518790 (2003-02-01), Wada et al.
patent: 6535019 (2003-03-01), De Santis
patent: 6552569 (2003-04-01), Wert
patent: 6586984 (2003-07-01), Radke
patent: 6611157 (2003-08-01), Usui
patent: 6614266 (2003-09-01), Ishii et al.
patent: 6617885 (2003-09-01), Lim et al.
patent: 6671201 (2003-12-01), Masuda
patent: 6762961 (2004-07-01), Eleyan et al.
patent: 6774673 (2004-08-01), Tsuboi et al.
patent: 6784700 (2004-08-01), Hunt et al.
patent: 6784717 (2004-08-01), Hunt et al.
patent: 6785107 (2004-08-01), Schmitt
patent: 6788125 (2004-09-01), Tomsio
patent: 6801064 (2004-10-01), Hunt et al.
patent: 6819137 (2004-11-01), Wang et al.
patent: 6829171 (2004-12-01), Ooishi
patent: 6836155 (2004-12-01), Shim
patent: 6859409 (2005-02-01), Hwang
patent: 6888381 (2005-05-01), Momtaz et al.
patent: 6940318 (2005-09-01), Wong
patent: 6946882 (2005-09-01), Gogl et al.
patent: 7038963 (2006-05-01), Lee
patent: 7106123 (2006-09-01), Kanno et al.
patent: 7151391 (2006-12-01), Chen et al.
patent: 7167027 (2007-01-01), Matsuo et al.
patent: 7276953 (2007-10-01), Peng et al.
patent: 7616513 (2009-11-01), Peng et al.
patent: 2003/0006801 (2003-01-01), Brownlow et al.
patent: 2003/0201800 (2003-10-01), Matsuo et al.
U.S. Appl. No. 10/964,040 entitled “Level Shifting Input Buffer Circuit,” filed Oct. 13, 2004.
U.S. Appl. No. 11/262,412 entitled “Memory Device, Current Sense Amplifier, and Method of Operating the Same,” filed Oct. 28, 2005.
USPTO Notice of Allowance for U.S. Appl. No. 10/964,040 dated May 18, 2007; 6 pages.
USPTO Advisory Action for U.S. Appl. No. 10/964,040 dated Apr. 18, 2007; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 10/964,040 dated Feb. 9, 2007; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/964,040 dated Sep. 5, 2006; 8 pages.
USPTO Advisory Action for U.S. Appl. No. 10/964,040 dated Jul. 27, 2006; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 10/964,040 dated May 8, 2006; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/964,040 dated Dec. 23, 2005; 14 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/262,412 dated Jun. 26, 2009; 6 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/262,412 dated Mar. 9, 2009; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/262,412 dated Sep. 26, 2008; 18 pages.
USPTO Advisory Action for U.S. Appl. No. 11/262,412 dated Jun. 30, 2008; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 11/262,412 dated Apr. 7, 2008; 19 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/262,412 dated Sep. 11, 2007; 16 pages.
USPTO Advisory Action for U.S. Appl. No. 11/262,412 dated Aug. 6, 2007; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 11/262,412 dated May 15, 2007; 14 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/262,412 dated Oct. 23, 2006; 12 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/870,289 dated Aug. 1, 2007; 4 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/870,289 dated Feb. 21, 2007; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/870,289 dated Oct. 19, 2006; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/870,289 dated Jun. 8, 2006; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/870,289 dated Jan. 10, 2006; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/870,289 dated Aug. 1, 2005; 7 pages.
Sinha et al., “High-Perfornace and Low-Voltage Sense-Amplifier Techniques for Sub-90nm SRAM,” 2003 IEEE, pp. 113-116.
USPTO Notice of Allowance for U.S. Appl. No. 10/229,481 dated Apr. 15, 2004; 7 pages.
USPTO Final Rejection for U.S. Appl. No. 10/229,481 dated Feb. 19, 2004; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/229,481 dated Oct. 17, 2003; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/676,539 dated Aug. 21, 2001; 5 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/229,481 dated May 5, 2003; 6 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 10/229,481 dated Apr. 4, 2003; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/228,436 dated Mar. 18, 2004; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/228,436 dated Nov. 13, 2003; 6 pages.
USPTO Advisory Action for U.S. Appl. No. 10/228,436 dated Oct. 8, 2003; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 10/228,436 dated Jul. 16, 2003; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/228,436 dated Mar. 27, 2003; 9 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/233,696 dated Apr. 22, 2004; 7 pages.
USPTO Advisory Action for U.S. Appl. No. 10/233,696 dated Mar. 26, 2004; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 10/233,696 dated Jan. 21, 2004; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 10/233,696 dated Oct. 3, 2002; 6 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/855,411 da

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low voltage interface circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low voltage interface circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage interface circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2745048

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.