Low voltage high performance semiconductor devices and methods

Details Low voltage high performance semiconductor devices and methods Low voltage high performance semiconductor devices and methods

2001-07-13

2002-12-10

Flynn, Nathan J. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000

Reexamination Certificate

active

06492693

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to low voltage, high performance semiconductor devices, such as MOS transistors for dynamic random access memory (DRAM) cells and logic applications, and to methods for fabricating such devices. More specifically, the present invention relates to methods for adjusting threshold voltage for high speed semiconductor transistor devices without the need for any additional masks.
BACKGROUND OF THE INVENTION
MOS processes typically begin with a lightly-doped P-type or N-type silicon substrate. For the sake of simplicity, the conventional MOS process will be described using P-type silicon as the starting material. If N-type silicon were used, the process steps would be virtually identical, with the exception that the dopant types would be reversed.
Silicon, the most commonly used semiconductor material can be made conductive by doping (introducing an impurity into the silicon crystal structure) with either an element such as boron, which has one less valence electron than silicon, or with elements such as phosphorus or arsenic, which have one more valence electron than silicon.
In the case of boron doping, electron “holes” become the charge carriers and the doped silicon is referred to as positive or P-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or N-type silicon. If dopants of opposite type conductivity are used, counter-doping will result, and the conductivity type of the most abundant impurity will prevail.
The P-well regions are oxidized using a conventional LOCOS (LOCal Oxidation of Silicon) step to create a silicon oxide layer. During the LOCOS process, the pad oxide serves as a stress relief layer. Alternatively, oxide growth and oxide deposition steps over silicon trench can replace the LOCOS step.
The channel regions of the future N-channel transistors are then exposed to a high-energy boron punch-through implant. This implant increases both source-to-drain breakdown voltage and the threshold voltage (V
t
), thus avoiding short-channel effects. The successful operation of MOS circuits is very dependent on the ability to control threshold voltage (V
t
). The threshold voltage (V
t
) of a transistor is the voltage necessary for turning the transistor on or off. Accurate control of V
t
is made possible by ion implantation. V, adjustment implantation into the channel usually takes place through a sacrificial gate oxide, before the growth of a gate oxide and deposition of the polysilicon for the gate electrodes.
In conventional MOS processes, after V
t
adjustment a layer of polysilicon is then deposited on top of the gate oxide using conventional means (e.g., chemical vapor deposition). The poly layer is then doped with phosphorus, and coated with a layer of tungsten silicide by various possible techniques (e.g., chemical vapor deposition, sputtering, or evaporation). A further photomask then patterns the silicide-coated polysilicon layer to form the transistor gates.
The N-channel source and drain regions are next is exposed to a relatively low-dosage phosphorus implant which creates lightly-doped drain (LDD) N-regions. Following the stripping of this mask, a layer of silicon dioxide or nitride is deposited on the wafer. An anisotropic etch and a subsequent optional isotropic etch of the silicon dioxide layer leave oxide spacers on the sides of each transistor gate.
A photomask then exposes the source and drain regions to a relatively high-dosage phosphorus or arsenic implant, which creates heavily-doped N+regions. A photomask is then used to define contacts which will pass through an isolation oxide, e.g., BPSG glass, layer to the poly structures or active area conductive regions below. A deposition of an aluminum metal layer follows. Another photomask is then used to pattern the aluminum layer for circuit interconnects. Using a blanket deposition process, the circuitry is then covered with one or more passivation layers. An additional photomask then defines bonding pad openings, which will expose bonding pad regions on the aluminum layer below. This completes a conventional MOS process.
The business of producing semiconductor devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance (speed) are key factors that determine success or failure. Each new generation of devices is expected to be faster and more compact than the generation it replaces.
In low voltage design, low threshold voltage (V
t
) is essential since the current drive is proportional to (V
g
−V
t
) where V
g
is the gate voltage. Because very precise quantities of impurity can be introduced using ion implantation, it is possible to maintain close control of V
t
. A problem arises, however, in connection with ion implantation for punch through prevention in such devices. Implanting a boron dopant, for example, for punch through prevention increases V
t
, and creates a barrier layer at the junction between the N+type source and drain regions and the underlying P-type substrate, thus increasing parasitic capacitance at this junction. This parasitic capacitance reduces the speed of the device.
A method is needed for adjusting V
t
, while minimizing parasitic capacitance and without introducing any additional photomasking steps.
SUMMARY OF THE INVENTION
The invention provides a low voltage, high speed semiconductor transistor device having low V
t
and reduced parasitic capacitance. Reduction in parasitic capacitance, and hence increase in speed, is achieved by shadowing out an angled punch through prevention ion implant between a transistor gate and adjacent structures to shadow out a portion of the implant. The resulting, minimally diffused implant results in a relatively lighter dose toward the edge of the transistor gate than the central regions of the source and drain, thus reducing V
t
and parasitic junction capacitance in those regions. The low V
t
and reduced parasitic capacitance devices may be produced together with higher V
t
devices elsewhere on the chip without any additional masking steps to make the low V
t
devices.


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