Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-10
2001-10-16
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S321000, C257S618000
Reexamination Certificate
active
06303960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductors, more specifically, the present invention relates to a process of manufacturing flash memory chips.
2. Description of the Related Art
Non-volatile semiconductor memories use a variety of semiconductor memory cell designs. One type of memory cell is a “flash” memory cell that is electrically erasable and electrically programmable. In other words, typical flash memory cells may be programmed, erased or read by a user. Once a flash memory cell is programmed, the data is stored in the flash memory cells until the data is erased or reprogrammed.
To achieve higher speed and higher densities, the physical dimension or size of each flash memory cell has been scaled down. A problem associated with reducing the size of a flash memory cell is the decreasing of the overlap area between the floating gate and the control gate. The size of the overlap area determines the coupling ratio between the control gate and floating gate, where the coupling ratio, which will be discussed later, affects the reliability of the flash memory. In short, a decrease in the overlap area may cause the flash memory to fail.
FIG. 1A
is a semiconductor structure
5
having a circuit layout of a conventional flash memory cell. A substrate
100
, a device isolation region
102
, a floating gate layer
106
, control gate layers
110
, a plurality of source regions
112
, and a drain region
114
are shown. A conventional method for increasing the overlap area is to deposit the control gate layer
110
in an angular shape as shown in
FIG. 1A. A
problem with this method is that when the overall physical size of the flash memory cell decreases, the area of the angular shaped control gate layer
110
also decreases. A decrease in the area of the angular shaped control gate layer
110
also causes the coupling ratio to decrease.
FIG. 1B
is a cross-sectional view of the semiconductor structure of
FIG. 1A
having a conventional flash memory layout. The semiconductor structure includes a substrate layer
100
, a drain region
114
, source regions
112
, a tunneling oxide layer
104
, floating gate layers
106
, oxide layers
108
, and controlling gate layers
110
. The semiconductor structure includes capacitance C
FG
, C
B
, C
S
, and C
D
. C
FG
indicates the capacitance between the floating gate layer
106
and the controlling gate layer
110
. C
B
indicates the capacitance between the floating gate layer
106
and the substrate
100
. C
S
is the capacitance between the floating gate layer
106
and the source region
112
. C
D
represents the capacitance between the floating gate layer
106
and the drain region
114
.
FIG. 1C
illustrates a distribution of capacitance within the semiconductor structure having a circuit layout of a conventional flash memory. The coupling ratio may be represent in the following equation using C
FG
, C
B
, C
S
, C
D
.
Coupling
Ratio
=
C
FG
C
FG
+
C
B
+
C
S
C
D
From the equation, if C
FG
is increased, the coupling ratio is also increased. Since enlarging the overlap area increases C
FG
, increasing in overlap area also increases the coupling ratio. However, enlarging the overlap area typically increases the size of the flash memory cell.
Therefore, there is a need to have a mechanism to increasing overlap area without increasing the size of the flash memory cell.
SUMMARY OF THE INVENTION
A method and an apparatus of a semiconductor process for manufacturing flash memory cells are described. The process may be used to fabricate flash memory chips having high coupling ratio between the floating gates and controlling gates.
In one embodiment, a first oxide layer is grown over a substrate and a first polysilicon layer is subsequently deposited over the first oxide layer. When the first polysilicon layer is properly etched and formed, an ONO (oxide nitride oxide) layer is deposited over the first polysilicon layer. Then, portions of the ONO layer and the first polysilicon layer are removed to form two nitride fences. A conformal shaped tunnel oxide layer is, subsequently, deposited over said nitride fences, some portions of the first oxide layer, and said substrate. After depositing of the tunnel oxide layer, a floating gate polysilicon layer, a second oxide layer, and a second polysilicon layer are, subsequently, deposited over the conformal shaped tunnel oxide layer. A portion of the second polysilicon layer, the second oxide layer, the floating gate layer, and the tunnel oxide layer are, subsequently, removed. Finally, a drain region and a source region are formed in the substrate.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
REFERENCES:
patent: 5391510 (1995-02-01), Hsu et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Taiwan Semiconductor Manufacturing Corporation
Wojciechowicz Edward
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