Low voltage electrically erasable programmable read only memory

Details Low voltage electrically erasable programmable read only memory Low voltage electrically erasable programmable read only memory

1980-05-27

1982-06-08

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, 357 23, G11C 1140

Patent

active

043342922

ABSTRACT:
An improved memory system is provided for charging and discharging a conductive plate such as a floating gate of a field effect transistor with a charge injector controlled by a low single polarity voltage pulse. In the system of the invention, the conductive plate may be a floating gate of a field effect transistor which also includes first and second or dual control gates. A single or double graded band gap layer, such as a silicon rich layer of silicon dioxide is disposed only between the floating gate and the first control gate forming a capacitor having a given capacitance with a larger capacitor disposed between the second control gate and the floating gate. These cells or transistors may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a 0 or a 1 depending upon whether a charge is stored on the floating gate. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array. To write and to erase a cell, a low single polarity voltage is employed. Several embodiments of the invention are disclosed including one embodiment wherein the dual gates are located on one side of the floating gate, a second embodiment which uses a diffusion in a semiconductor substrate as one of the control gates and a third embodiment wherein one of the control gates is disposed on one side of, or above, the floating gate and the other control gate is disposed on the other side of, or below, the floating gate near the surface of the channel region of the transistor.

REFERENCES:
patent: 3825946 (1974-07-01), Frohman-Bentchkowsky
patent: 4161039 (1979-07-01), Rossler
IBM Technical Disclosure Bulletin, Floating Gate Nonvolatile Memory Cell,vol. 22, No. 6, Nov. 1979, pp. 2403-2404.

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