Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-07-08
2000-12-05
Picard, Leo P.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257314, 438259, 438262, 438264, 438266, H01L 218247
Patent
active
061570583
ABSTRACT:
A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.
REFERENCES:
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4561004 (1985-12-01), Koo et al.
patent: 5198380 (1993-03-01), Harari
patent: 5262987 (1993-11-01), Kojima
patent: 5519653 (1996-05-01), Thomas
patent: 5591652 (1997-01-01), Matsushita
Abbas et al. "N-Channel IGFET Design Limitations Due To Hot Electron Trapping" IEDM 1975.
Ning et al."Emission Probability of hot electrons from silicon into silicon dioxide" J. Applied Physics, 1997, vol. 48, p. 286-293.
"A Fully-Decoded 2048-Bit Electrically-Programmable MOS-ROM" by Froham-Bentchkowsky, 1971, IEEE International Solid State Circuit Conf, p. 80-81.
"FAMOS--A New Semiconductor Charge Storage Device", Solid State Electronics, 1974, vol. 17, p. 517-529.
"Operation And Characterization of N-channel EPROM Cells", Barnes et al, 1976, IEDM, p. 177.
"High Performance MOS EPROMs Using A Standard-Gate Cell", P. Salsbury in 1977 ISSCC, p. 186-187.
"Lucky-Electron Model of Channel Hot Electron Emission", Cheming Hu in IEDM 1970, p. 223-226.
"A128K Flash EEPROM Using Double-Polysilicon Technology", G. Samachusa et al 1987 IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, p. 676-683.
"A Flash-Erase EEPROM Cell With An Asymmetric Source And Drain Structure" H. Kume et al, Technical Digest of the IEEE International Electron Device Meeting, Dec. 1987, p. 560-563.
Kynett et al. "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory",Tech Digest of IEEE International Electron Dev. Mtg, Dec. 1987, p. 1157-1162.
J. Kupec et al. "Triple Level Polysilicon E.sup.2 PROM With Single Transistor PerBit",1980 IEDM Technical Digest, p. 602-606.
A. T. Wu, "A Novel High Speed 5-Volt Programming EPROM Structure With Source Side Injection", 1986 IEDM Technical Digest, p. 584-587.
Ackerman Stephen B.
Duong Hung Van
Halo LSI Design & Device Technology, Inc.
Picard Leo P.
Pike Rosemary L. S.
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