Low voltage dual-well MOS device having high ruggedness, low on-

Details Low voltage dual-well MOS device having high ruggedness, low on- Low voltage dual-well MOS device having high ruggedness, low on-

1999-06-03

2000-10-24

Dutton, Brian

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257335, H01L 2976

Patent

active

061371394

ABSTRACT:
An improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises a semiconductor substrate on which is disposed a doped upper layer of a first conduction type. The upper layer includes at its upper surface a blanket implant of the first conduction type, a heavily doped source region of the first conduction type, and a heavily doped body region of a second and opposite conduction type. The upper layer further includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the source and body regions. The first well region underlies the second well region and merges with the blanket implant to form a heavily doped neck region that abuts the second well region at the upper surface of the upper layer. A gate comprising a conductive material separated from the upper layer by an insulating layer is disposed on the upper layer overlying the heavily doped neck region. A process for forming an improved low-voltage MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery characteristics comprises providing a semiconductor substrate that includes a doped upper layer of a first conduction type, and implanting a blanket dopant of the first conduction type in an upper surface of the upper layer. A gate comprising a conductive material and an insulating layer is formed on the upper layer of the substrate, and a doped first well region of the first conduction type and a doped second well region of a second and opposite conduction type are formed by implanting dopants of first and second conduction types through a common window into the upper surface of the upper layer. The first well region underlies the second well region and merges with the blanket implant, forming a heavily doped neck region underlying the gate and abutting the second well region at the upper surface of the upper layer. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in the second well region at the upper surface of the upper layer.

REFERENCES:
patent: 4975751 (1990-12-01), Beasom
patent: 5091336 (1992-02-01), Beasom
patent: 5661314 (1997-08-01), Merrill et al.
patent: 5757033 (1998-05-01), Ajit
patent: 5925910 (1999-07-01), Menegoli

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