Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-11-16
2004-05-04
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C327S108000
Reexamination Certificate
active
06731135
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data signaling devices, and more particularly, to low voltage differential signaling devices having improved impedance and performance characteristics by virtue of a novel mid-point biasing scheme.
BACKGROUND OF THE INVENTION
U.S. application Ser. No. 09/626,264, filed Jul. 25, 2000 and entitled “Low Voltage Differential I/O Device and Method,” commonly owned by the present assignee, the contents of which are incorporated herein by reference, dramatically advanced the state of the art of signaling devices, and more particularly, low voltage differential signaling (LVDS) device technology. An example of an LVDS device according to the principles of the above-mentioned application is illustrated in FIG.
1
. As shown in
FIG. 1
, when a differential signal having a first logic state, for example a “positive state”, is desired to be transmitted, input D+ is set to a positive voltage (e.g. Vdd or 2.5V) and input D− is set to a zero voltage (e.g. Vss or 0V). This causes PFET Q
1
and NFET Q
4
to turn on and PFET Q
2
and NFET Q
3
to turn off, thus causing resistor Rd
2
to be oriented in a conduction path between nodes A and B through transistors Q
1
and Q
4
such that a positive differential voltage of about 330 mV from common mode is established between true and complement signal lines
102
and
104
due to the positive voltage drop across resistor Rd
2
.
When a differential signal having a second logic state, for example a “negative state”, is desired to be transmitted, input D+ is set to a zero voltage (e.g. Vss or 0V) and input D− is set to a positive voltage (e.g. Vdd or 2.5V). This causes PFET Q
2
and NFET Q
3
to turn on and PFET Q
1
and NFET Q
4
to turn off, thus causing resistor Rd
2
to be oriented in a conduction path between nodes A and B through transistors Q
2
and Q
3
such that a negative differential voltage of about 330 mV from common mode is established between the true and complement signal lines
102
and
104
due to the negative voltage drop across resistor Rd
2
.
An advantage of the invention of the above-mentioned application is that the driver impedances Z
1
and Z
2
of driver
100
will be the same for all logic states as well as for common mode due to the operation of transistors Q
1
, Q
2
, Q
3
and Q
4
and the constant impedances provided by Rd
1
, Rd
2
and Rd
3
. Moreover, the desired common mode voltage is easily established in both logic states by operation of the driver itself when either transistors Q
1
and Q
4
are turned on and Q
2
and Q
3
are turned off or transistors Q
2
and Q
3
are turned on and Q
1
and Q
4
are turned off. Accordingly, it should be apparent that the common mode voltage Vcm will be determined by the difference between the voltage at nodes A and B regardless of which pairs of transistors Q
1
/Q
4
and Q
2
/Q
3
are turned on and which are turned off.
Another advantage of the invention of the above-mentioned application is that driver output impedance problems are substantially reduced. In particular, for long transmission lines, because the output impedance is ideally matched with the transmission lines, noise reflections are reduced. For short transmission lines, energy arising from stimulation of parasitic inductors is absorbed by the back termination Rd
2
and the parasitic capacitance, thus providing sufficient dampening against ringing on the transmission lines.
Yet another advantage of the invention of the above-mentioned application is that the resistor Rd
2
of this configuration can be used as a termination resistor when the transmission lines are being used for bidirectional signaling. For bidirectional signaling mode, transistors Q
1
, Q
2
, Q
3
and Q
4
are driven so as to be turned off, which leaves a parallel resistance of R
term
and Rd
2
between the true and complement signal lines
102
and
104
, and allows the voltage between the lines to float to around to the common mode voltage as established by the generator. Accordingly, Rd
2
in this mode acts as a receiver termination resistor R
term
.
However, as fabrication technologies have advanced, and as processes continue to reduce feature sizes below 0.25 um, other problems have arisen that are not entirely solved by the above-mentioned application.
For example, although the single-ended output impedance Z
0
will be about the same in both output logic states, it can still range about as high as 150 ohms in some applications. This output impedance is difficult to reduce without increasing power substantially (e.g. by 50%), or reducing the output swing below the specified level. However, it would be desirable to lower the output impedance to about 50 ohms to ideally match the load both for differential and single ended reflections.
Further, when porting the same circuit design to different fabrication processes, process tracking may be needed to adjust and re-design the values of different circuit components. This is because the common-mode voltage is derived from a voltage division between components whose resistances may vary from process to process. Meanwhile, the common-mode voltage should desirably be around 1.2 V for all circuits, independent of fabrication process, so as to provide the maximum ground level sensitivity. Accordingly, it would be desirable to have a single circuit design that can provide the desired common-voltage for many different fabrication processes.
SUMMARY OF THE INVENTION
The present invention relates to low voltage differential signaling circuits and schemes. According to one aspect of the invention, a mid-point biasing scheme is employed that maintains a desired common mode voltage across all logic states signaled by the circuit. In one driver implementation, separate conduction paths are used to signal respective logic states on a pair of differential signal lines. A common pair of resistors are provided in the conduction path between the two signal lines. The midpoint between the pair of resistors is tied to the desired common mode voltage. A midpoint bias circuit is coupled to a variable resistance in the conduction path so as to maintain the desired common mode voltage by virtue of a voltage division so as to minimize the amount of non-conduction path current at the mid point node. In one example, a replica circuit further provides an anticipated midpoint voltage to the midpoint bias circuit for comparison to the desired midpoint voltage. The midpoint bias circuit adjusts the variable resistance in accordance with the comparison. In addition to providing stable common mode voltage across all signaling states, the circuit configuration further provides desired output impedance characteristics. Moreover, by virtue of its design, the circuit can be ported to various fabrication processes without process tracking as required by prior designs.
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National Semiconductor “Product Folder, DS90LV048A”, Jun. 1999.
National Semiconductor “LVDS Products, LVDS Product Family Introductions”, Jun. 1999.
National Semiconductor “Product Folder, DS90LV031A”, Jun. 1999.
Artisan Components Inc.
Cho James H
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