Low voltage data path in memory array

Details Low voltage data path in memory array Low voltage data path in memory array

2007-05-09

2008-11-11

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S190000, C365S207000

Reexamination Certificate

active

07450454

ABSTRACT:
A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

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PCT Search report and Written Opinion for corresponding PCT Application No. PCT/US08/61707 mailed Jul. 25, 2008.

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