Low-voltage current mode logic circuits and methods

Details Low-voltage current mode logic circuits and methods Low-voltage current mode logic circuits and methods

2002-06-14

2004-02-17

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S075000

Reexamination Certificate

active

06693464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to Current Mode Logic (CML) and Emitter Coupled Logic (ECL) circuits.
2. Related Art
Current mode logic (CML) circuits have many applications including multiplexing, frequency division, and implementing logical functions such as AND, NAND, OR, and XOR.
FIG. 1
is a block diagram depicting a prior art CML circuit
100
. The CML circuit
100
comprises a buffer/inverter module
102
, an emitter follower module
104
and a two-level CML gate
106
. The buffer/inverter module
102
is used to drive the transistors Q
9
and Q
10
of the two-level CML gate
106
. The buffer/inverter module
102
may be replaced with another module (e.g., a two-level CML gate) that is suitable for driving the transistors Q
9
and Q
10
. The emitter follower module
104
is used to ensure that the buffer/inverter module
102
is compatible with the direct current (DC) level required for the base terminals B
9
and B
10
of the transistors Q
9
and Q
10
, respectively.
The buffer/inverter module
102
comprises transistors Q
1
and Q
2
and resistors R
1
and R
2
. The transistor Q
1
has a base terminal B
1
, a collector terminal C
1
and an emitter terminal E
1
. The transistor Q
2
has a base terminal B
2
, a collector terminal C
2
and an emitter terminal E
2
. The resistor R
1
is coupled between the voltage source Vs and the collector terminal C
1
. The resistor R
2
is coupled between the voltage source Vs and the collector terminal C
2
. The emitter terminal E
1
and the emitter terminal E
2
are coupled to each other and to a current source
110
.
The emitter follower module
104
comprises transistors Q
3
and Q
4
. The transistor Q
3
has a base terminal B
3
, a collector terminal C
3
and an emitter terminal E
3
. The base terminal B
3
is coupled to a node
124
between the resistor R
2
and the collector terminal C
2
. The emitter terminal E
3
is coupled to a current source
112
. The transistor Q
4
has a base terminal B
4
, a collector terminal C
4
and an emitter terminal E
4
. The base terminal B
4
is coupled to a node
122
between the resistor R
1
and the collector terminal C
1
. The emitter terminal E
4
is coupled to a current source
114
. The collector terminals C
3
and C
4
are coupled to the voltage source Vs.
The two-level CML gate
106
comprises transistors Q
5
, Q
6
, Q
7
, Q
8
, Q
9
, and Q
10
as well as the resistors R
5
, R
6
, R
7
, R
8
. The transistor Q
5
has a base terminal B
5
, a collector terminal C
5
, and an emitter terminal E
5
. A resistor R
5
couples between collector terminal C
5
and the voltage source Vs. The transistor Q
6
has a base terminal B
6
, a collector terminal C
6
, and an emitter terminal E
6
. A resistor R
6
couples between collector terminal C
6
and the voltage source Vs. The emitter terminals E
5
and E
6
are coupled to each other.
The transistor Q
7
has a base terminal B
7
, a collector terminal C
7
, and an emitter terminal E
7
. A resistor R
7
couples between collector terminal C
7
and the voltage source Vs. The transistor Q
8
has a base terminal B
8
, a collector terminal C
8
, and an emitter terminal E
8
. A resistor R
8
couples between collector terminal C
8
and the voltage source Vs. The emitter terminals E
7
and E
8
are coupled to each other.
The transistor Q
9
has a base terminal B
9
, a collector terminal C
9
, and an emitter terminal E
9
. The base terminal B
9
is coupled to a node
128
between the emitter terminal E
4
and the current source
114
. The emitter terminal E
9
is coupled to a current source
116
. The collector terminal C
9
is coupled to a node
130
between the emitter terminal E
5
and the emitter terminal E
6
.
The transistor Q
10
has a base terminal B
10
, a collector terminal C
10
, and an emitter terminal E
10
. The base terminal B
10
is coupled to a node
126
between the emitter terminal E
3
and the current source
112
. The emitter terminal E
10
is coupled to a current source
116
. The collector terminal C
10
is coupled to a node
132
between the emitter terminal E
7
and the emitter terminal E
8
.
When the CML circuit
100
is in operation, the base terminals B
1
and B
2
receive inputs for driving the two-level CML gate
106
. The two-level CML gate
106
may receive inputs via base terminal B
5
, B
6
, B
7
, and B
8
, and may provide output via nodes
151
-
154
. The minimum voltage supply required to operate the CML circuit
100
is equal to the sum of the voltage drops across the resistor R
1
, the base-emitter connection for the transistor Q
4
, the base-emitter connection for the transistor Q
9
, and the current source
116
. This minimum supply voltage requirement is typically around 2.1 Volts for a circuit temperature of 30° C. and around 2.3 Volts for a circuit temperature of−30° C.
Current Mode Logic circuits such as, for example, CML circuit
100
, are frequently used in portable wireless devices where there is a continuing need for lower voltage supply requirements (e.g., 1.8 Volts or less). The need for lower voltage supply requirements is especially great for small wireless devices that run at high frequencies (e.g., over 1 GHz). Therefore, it is desirable to address these and/or other needs related to CML circuits.
SUMMARY
The invention provides a low voltage CML circuit. In one embodiment of the invention, a current mode logic (CML) circuit includes an emitter follower circuit, a CML gate, and a Schottky diode that is coupled between the emitter follower circuit and the CML gate.


REFERENCES:
patent: 3974402 (1976-08-01), Fett et al.
patent: 4488063 (1984-12-01), Lee
patent: 4605871 (1986-08-01), Price et al.
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 62071329 (1987-04-01), None

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