Low voltage CMOS SRAM

Details Low voltage CMOS SRAM Low voltage CMOS SRAM

1996-12-31

1998-01-06

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 257903, 257274, G11C 1100

Patent

active

057062269

ABSTRACT:
A complementary-metal-oxide-semiconductor, static-random-access-memory cell has two pairs of n-channel and p-channel transistors in complementary symmetry, push-pull arrangement. One pair of complementary transistors stores the binary state of the memory cell, and the other pair of complementary transistors stores the complement of the binary state of the memory cell. Both transistors in each of the complementary pairs of complementary transistors in the memory cell have nearly equal current carrying capacity and provide a voltage trip point for a change of state of the memory cell equal to approximately 1/2 the bias voltage across the memory cell. Complementary word lines and bit lines select a memory cell for reading or writing. The wordline control gates have complementary transistors, and those complementary transistors push or pull current to the memory cell in parallel to minimize the effect of transistor threshold voltage on the flow of current to the complementary transistors in the memory cell. A pair of transmission gates are connected one each to each of the complementary bit lines. Each transmission gate has a pair of complementary transistors and an actuation input. The transmission gates upon actuation passing voltages on complementary bit-lines indicative of the state of the memory cell.

REFERENCES:
patent: 5523966 (1996-06-01), Idei et al.
patent: 5526303 (1996-06-01), Okajima
patent: 5623440 (1997-04-01), Saito
Sung-Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits; Analysis & Design", McGraw-Hill, 1995, Chapter 2.

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