Low voltage CMOS circuit for on/off chip drive at high voltage

Details Low voltage CMOS circuit for on/off chip drive at high voltage Low voltage CMOS circuit for on/off chip drive at high voltage

1998-01-08

2000-02-29

Tokar, Michael

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 81, 326 80, 326 33, 326 83, 326 58, 326 86, 326121, 326 57, 326 68, H03K 190175, H03K 19094, H03K 19003, H03K 1900

Patent

active

060313943

ABSTRACT:
A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.

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