Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-03-11
2004-10-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C327S543000, C307S010400, C363S060000
Reexamination Certificate
active
06806760
ABSTRACT:
RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2002-20888, filed on Apr. 17, 2002, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuit devices, and, more particularly, to booster circuits for semiconductor integrated circuit devices.
As lower power consumption has been desired in semiconductor integrated circuit devices, power supply voltage has been increasingly lowered to provide lower power consumption. However, semiconductor memory devices often include circuits that need voltages higher than the power supply voltage. For this reason, booster circuits are often included in semiconductor integrated circuit devices to provide higher voltages.
Referring to
FIG. 1
, a conventional booster circuit
10
generates a higher voltage than a power supply voltage VCC and comprises switches SW
1
, SW
2
, SW
3
, and SW
4
and a capacitor C
1
. The switches SW
1
and SW
4
are controlled by a control signal P
2
, and the switches SW
2
and SW
3
are controlled by a control signal P
1
. The control signals P
1
and P
2
are alternately oscillating signals.
In operation, when the control signal P
1
is at a high level and the control signal P
2
is at a low level, a node NDA is coupled to a ground node GND through the switch SW
3
, and a node NDB is coupled to the power supply voltage VCC through the switch SW
2
. Consequently, the nodes NDA and NDB are charged to the voltage of the ground node GND and the voltage of the power supply node VCC, respectively. When the control signal P
1
goes low and the control signal P
2
goes high, a voltage of the node NDB is increased from VCC to 2 VCC by the capacitor C
1
. When the control signal P
1
has a low-to-high transition and the control signal P
2
has a high-to-low transition, the nodes NDA and NDB are charged to the voltage of the ground node GND and the power supply node VCC, respectively.
In general, efficiency is a ratio of output power to input power. As output power may be determined by subtracting power loss from input power, efficiency (in percentage) may be expressed as (output/(output+loss))*100. Output may indicate an amount of charge that is transferred to a high voltage terminal VP at pumping, while loss may represent the amount of charge that is consumed at charging. Accordingly, pump efficiency of a booster circuit as shown in
FIG. 1
may be expressed as follows:
Pump
efficiency
=
C
(
2
VCC
-
VP
)
C
{
VCC
-
(
VP
-
VCC
)
}
+
C
(
2
VCC
-
VP
)
×
100
(
1
)
In Equation (1), “C” is a capacitance value of the capacitor C
1
. The conventional booster circuit
10
illustrated in
FIG. 1
has a pump efficiency of about 50%.
To obtain a boosted voltage using a lower supply voltage using the circuit of
FIG. 1
, input current to be consumed typically is greater than current to be pumped. Therefore, the pump efficiency of the conventional booster circuit of
FIG. 1
is always less than “1.” Generally, the higher the pump efficiency, the less input current needed to produce constant output current. Accordingly, it is generally desirable to develop a booster circuit whose pump efficiency is high.
SUMMARY OF THE INVENTION
In some embodiments of the present invention, a voltage booster circuit includes first and second capacitors and a switch circuit coupled to the first and second capacitors. The switch circuit is operative to apply a power supply across the first and second capacitors in series responsive to a first signal to thereby charge the first and second capacitors and to couple the first and second capacitors in parallel between an output terminal and a power supply node of the power supply responsive to deassertion of the first signal and assertion of a second signal to thereby boost a voltage at the output terminal. The first and second signals may be alternately asserted in a succession of time periods, e.g., the first and second signals may be asserted in respective non-overlapping time periods.
In some embodiments, the switch circuit includes a first switch operative to couple and decouple a first terminal of the first capacitor to and from a ground node responsive to the first signal; a second switch operative to couple and decouple the first terminal of the first capacitor to and from a power supply node responsive to the second signal; a third switch operative to couple and decouple a second terminal of the first capacitor to and from the output terminal responsive to the second signal; a fourth switch operative to couple and decouple the second terminal of the first capacitor to and from a first terminal of the second capacitor responsive to the first signal; a fifth switch operative to couple and decouple the first terminal of the second capacitor to and from the power supply node responsive to the second signal; a sixth switch operative to couple and decouple a second terminal of the second capacitor to and from the power supply node responsive to the first signal; and a seventh switch operative to couple and decouple the second terminal of the second capacitor to and from the output terminal responsive to the second signal.
In further embodiments, the booster circuit further includes a third capacitor having a first terminal configured to receive the first signal. The first capacitor has a first terminal configured to receive the second signal. The switch circuit includes: a first transistor having a current path that is coupled between a second terminal of the first capacitor and a first terminal of the second capacitor and that is controlled responsive to the first signal; a second transistor having a current path that is coupled between the second terminal of the first capacitor and the output terminal and that is controlled responsive to the second signal; a third transistor having a current path that is coupled between a second terminal of the second capacitor and the output terminal and that is controlled responsive to the second signal; a fourth transistor having a current path that is coupled between the second terminal of the second capacitor and a power supply node and that is controlled responsive to the first signal; a fifth transistor having a current path that is coupled between a second terminal of the third capacitor and the power supply node and that is controlled responsive to a voltage at the second terminal of the first capacitor; and a sixth transistor having a current path that is coupled between the first terminal of the second capacitor and a second power supply node and that is controlled responsive to a third signal that is a logical complement of the second signal.
In additional embodiments of the present invention, a booster circuit includes first and second capacitors and an output terminal. A first switch circuit couples the first and second capacitors in series between a power supply node and a ground node during a first period to charge the first and second capacitors. A second switch circuit couples the first and second capacitors in parallel between the output terminal and a power supply node during a second period to pump current to the output terminal. The first switch circuit may include: a first switch which is coupled between first terminals of the first and second capacitors; a second switch which is coupled between a second terminal of the first capacitor and a ground node; and a third switch which is coupled between a second terminal of the second capacitor and the power supply node. The first, second and third switches operate responsive to a first signal. The second switch circuit may include: a fourth switch which is coupled between the second terminal of the first capacitor and the power supply node; a fifth switch which is coupled between the one terminal of the first capacitor and the output terminal; a sixth switch which is coupled between the one terminal of the second capacitor and the power supply node; and a seventh switch which is coupled betw
Callahan Timothy P.
Englund Terry L.
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
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