Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-05-17
2005-05-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S573000, C438S595000, C438S648000
Reexamination Certificate
active
06893962
ABSTRACT:
A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNyis deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.
REFERENCES:
patent: 5925225 (1999-07-01), Ngan et al.
patent: 6080285 (2000-06-01), Liu et al.
patent: 6150720 (2000-11-01), Yamaha et al.
patent: 6156647 (2000-12-01), Hogan
patent: 6291342 (2001-09-01), Lee et al.
patent: 6303490 (2001-10-01), Jeng
patent: 6383915 (2002-05-01), Su et al.
patent: 6403465 (2002-06-01), Liu et al.
patent: 6432819 (2002-08-01), Pavate et al.
Li Weidan
Tripathi Prabhakar P.
Wang Zhihai
LSI Logic Corporation
Luedeka Neely & Graham
Luu Chuong Anh
Smith Matthew
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