Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-10-03
2006-10-03
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S362000
Reexamination Certificate
active
07115951
ABSTRACT:
In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.
REFERENCES:
patent: 4102714 (1978-07-01), DeBar et al.
patent: 5949094 (1999-09-01), Amerasekera
patent: 6388292 (2002-05-01), Lin
patent: 6593157 (2003-07-01), Chen et al.
patent: 6605493 (2003-08-01), Yu
patent: 1-251663 (1989-10-01), None
Beek Marcel ter
Concannon Ann
Hopper Peter J.
Mirgorodsky Yuri
Vashchenko Vladislav
National Semiconductor Corporation
Vollrath Jurgen
Vu Hung
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