Low triggering N MOS transistor for ESD protection working...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S173000, C257S357000, C257S360000, C257S491000

Reexamination Certificate

active

07154150

ABSTRACT:
An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+
−/p−

+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n− well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region. The third embodiment forms a second NPN parasitic bipolar using the third N+ region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n+ region to the first p+ region and the second n+ region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.

REFERENCES:
patent: 5043782 (1991-08-01), Avery
patent: 5519242 (1996-05-01), Avery
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5689133 (1997-11-01), Li et al.
patent: 5898205 (1999-04-01), Lee
patent: 5969923 (1999-10-01), Avery
patent: 6066879 (2000-05-01), Lee et al.
patent: 6458632 (2002-10-01), Song et al.
patent: 6787856 (2004-09-01), Hu et al.
The paper by Amerasekera et al., “Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with th ESD/EOS Performance of a 0.25 μm CMOS Process,” 1996, IEEE, IEDM 96-893 to 96-896.
The paper by Charvaka Duvvury, “ESD : Design for IC Chip Quality and Reliability,” 2000 IEEE, pp. 251-259.
The paper by Polgreen et al., “Improving the ESD Failure Thershol, of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow,” IEEE Transactions on Electron Devices, vol. 39, No. 2, Feb. 1992, pp. 379-388.
The paper by Notermans et al., “The Effect of Silicide on ESD Performance,” IEEE 1999, 37th Annual International Reliability Physics Symposium, San Diego, CA, pp. 154-158.
Chen et al., “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,”IEEE Trans. 2 Electron Devices, vol. 45, No. 12, Dec. 1998, pp. 2448-2456.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low triggering N MOS transistor for ESD protection working... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low triggering N MOS transistor for ESD protection working..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low triggering N MOS transistor for ESD protection working... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3689660

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.