Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-10-31
2003-09-23
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S098000, C327S534000
Reexamination Certificate
active
06624663
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to clock generation in an integrated circuit. More particularly, the present invention relates to the minimization of clock skew and jitter in a clock distribution network. Still more particularly, the present invention relates to a clock distribution network design in which clock drivers are designed using silicon-on-insulator techniques to render the drivers relatively insensitive to power supply variations and fluctuations to thereby reduce the effects of skew and jitter in the distributed clock signals.
2. Background of the Invention
One of the critical design elements in modern processor chips and other very large scale integrated circuits is the manner in which the clock signals are distributed within the integrated circuit. Most digital circuits require a clock signal to operate, and data in a digital circuit typically is latched, processed, and output on one or more edges (i.e., the rising edge, the falling edge, or both) of the clock signal. Thus, without a good quality clock signal, most digital circuits will not operate properly, or will operate erratically.
In modem processor designs, and other very large scale integrated circuits, the clock signal may need to be distributed to relatively large areas of the die, because of the layout of the digital circuitry. To enable the clock signal to be effectively transmitted over long distances, it is common to use clock drivers that are distributed throughout the die. Without the clock drivers, the clock signal may attenuate or degrade to such an extent that the receiving digital circuitry cannot operate properly. This problem is compounded as designers reduce the power supply voltage. Thus, more than ever, clock drivers are required to insure that a high quality clock signal is delivered to the digital circuitry in the integrated circuit.
As even the most casual observer is aware, the clock speed of modem digital circuitry has increased at an astonishing rate. It has become commonplace for processors to meet or exceed clock speeds of 1 Gigahertz. Clock speeds have become sufficiently high that the problem of delivering a high quality clock signal to all digital circuits in a large integrated circuit, such as a processor, is becoming increasingly challenging. A processor with a 1GHz clock means that 1 billion clock pulses must be transmitted to each digital circuit device on the die each second. Moreover, to avoid problems with clock skew and jitter, a relatively stable clock signal must arrive at the digital circuits at substantially the same time. If the clock signals do not arrive at each digital circuit at virtually the same time, drastic consequences may result, which could cause the processor to operate improperly or to fail. As an example, most processors include a processor core and an on-chip cache memory. According to normal convention, the processor core saves and retrieves data to the cache memory during normal processor operations. The protocol by which data is read from and written to the cache is precisely set to maximize system efficiency. During a read cycle, for example, the processor core expects that data from the cache will be made available on a predetermined number of clock cycles after the read request. If the cache memory receives the clock signal at a point in time that is delayed relative to the processor core, the cache memory may not have the data available when expected. The processor core may nonetheless interpret the state of the signal lines as the read data, and thus may accept invalid data. Such a result could be catastrophic.
To avoid these and other errors that result from clock skew and clock jitter, clock distribution networks are implemented to ensure some acceptable level of synchronism between the digital circuitry. Typically, a clock distribution tree is provided in the integrated circuit to distribute the clock signal throughout the die. As shown in
FIG. 1A
, the clock distribution tree distributes one or more clock signals from a common clock generator
10
, which is specially placed on the die
5
. An example of a portion of one branch of a clock distribution tree is shown in
FIG. 1A
, for purposes of illustration. As shown in
FIG. 1A
, a plurality of clock repeaters (or clock drivers)
15
are provided in each branch to regenerate and re-transmit the clock signal to the digital circuitry on the die to ensure that each digital circuit receives high quality clock signals. Five clock drivers are shown in each of the two branches depicted in
FIG. 1A
, providing clock signals to the upper right die region and the lower right die region. Each clock driver defines another “stage” of the clock distribution tree, and each clock distribution stage produces a limited amount of gain to the clock signal. The number of clock distribution stages is dictated by the area covered on the die, and the load (i.e., the number of devices that receive the clock signal on each branch). Each stage of the clock distribution network introduces a risk that a variation will be produced that will result in the clock signals not being synchronized between different distribution branches. To minimize this risk, equidistant signal paths or traces generally are used to connect each of the digital circuits to the clock generator
10
. By using signal paths of equal length, the propagation delay is minimized. To further minimize the risk that different distribution branches may have a different propagation delay, each clock driver
15
is identically constructed, and drivers are located uniformly in the branches.
According to conventional techniques, the clock drivers
15
are implemented using inverters, which comprise a relatively simple circuit design. An example of a standard clock inverter used in digital circuit design is shown in FIG.
2
A. As shown in
FIG. 2A
, the conventional inverter comprises a pFET (p-junction field effect transistor) and an nFET (n-junction field effect transistor) with their gates tied to a common clock input terminal and their drains tied to a common clock output terminal. The Source terminal of the pFET connects to the voltage power supply V
DD
, while the Source of the nFET connects to V
SS
. When a low voltage (a binary “0”) appears at the clock input terminal, the nFET is non-conducting, while the pFET conducts the voltage power supply V
DD
at the Source terminal to the Drain terminal, which produces a high voltage (a binary “1”) at the clock output terminal. Conversely, when the input clock terminal is at a high voltage (a binary “1”), the pFET is non-conducting, and the nFET conducts, causing the low voltage V
SS
(a binary “0”) to appear at the clock output terminal.
Despite the precautions taken in designing clock distribution networks, propagation delays still occur among different clock paths. These propagation delays result from several factors. One of the primary factors that cause this propagation delay is local variation in the power supply voltage. These variations in power supply voltage occur due to the load experienced within a particular region. Thus, the region of the CPU core may be drawing more power than another area, such as the cache memory. This may cause the CPU core region, for example, to experience a reduction in the power supply voltage by a significant amount (which could differ by as much as 15-25% across different die regions). Generally, the higher the power supply voltage, the faster the signal will propagate through the clock driver (or inverter). Thus, these voltage fluctuations produce non-uniform propagation delays that result from heavier circuit operation in a particular region of the die. Other factors, which also can cause propagation delays, are temperature gradients, process variations, and the like.
Some attempts have been made to mitigate the propagation delay caused by these environmental and process
Bailey Daniel William
Dever Daniel E.
Preston Ronald P.
Chang Daniel
Hewlett--Packard Development Company, L.P.
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