Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-04-09
1998-02-17
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257344, 257345, 257404, 257408, H01L 27088
Patent
active
057194220
ABSTRACT:
Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.
REFERENCES:
patent: 4017888 (1977-04-01), Christie et al.
patent: 4315781 (1982-02-01), Henderson
patent: 4485390 (1984-11-01), Jones et al.
patent: 4984045 (1991-01-01), Matsunaga
patent: 5019520 (1991-05-01), Komori
patent: 5060033 (1991-10-01), Takeuchi
patent: 5075242 (1991-12-01), Nakahara
patent: 5166765 (1992-11-01), Lee et al.
patent: 5208171 (1993-05-01), Ohmi
patent: 5243210 (1993-09-01), Naruke
patent: 5289027 (1994-02-01), Terrill et al.
patent: 5338697 (1994-08-01), Aoki et al.
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5374839 (1994-12-01), Jeon et al.
patent: 5378909 (1995-01-01), Chang et al.
Skotnicki, Tomasz, Merckel, Gerard, and Pedron, Thierry, "Anomalous Punchthrough in ULSI Buried-Channel Mosfet's", pp. 2548-2556, vol. 36, IEEE Translations on Electronic Devices, Nov. 1989.
Konaka, Masami, Iwai, Hiroshi, and Nishi, Yoshio, "Suppression of Anomalous Drain Current in Short Channel Mosfet", Japanese Journal of Applied Physics, Supplement 18-1, vol. 18, Tokyo Japan, 1979.
Nagai, Ryo, Umeda, Kazunori, Takeda, Eiji, "Low-Voltage High-Gain 0.2 .mu.m N-Channel Metal Oxide Semiconductor Field Effect Transistors Channel Counter Doping with Arsenic", pp. 434-437, Japanese Journal of Applied Physics, vol. 32, No. 1B, Tokyo, Japan, Jan. 1993.
Patent Abstracts of Japan, vol. 012, No. 204, (E-620), Jun. 11, 1988, and JP-A-63 003448, (NEC Corp.) Jan. 8, 1988.
Patent Abstracts of Japan, vol. 011, No. 309, (E-547) Oct. 8, 1987, and JP-A-62 101068 (HITACHI LTD) May 11, 1987.
Patent Abstracts of Japan, vol. 008, No. 025, (E-225), Feb. 2, 1984, and JP-A-58 188160 (SANYO DENKI KK) Nov. 2, 1983.
Yan, R. H.; Lee, K. F.; Jeon, D.Y.; Kim, Y. O.; Park, B. G.; Pinto, M. R.; Rafferty, C. S.; Tennant, D. M.; Westerwick, E. H.; Chin, G. M.; Morris, M.D.; Early, K.; Mulgrew, P.; Mansfield, W. M.; Watts, R. K.; Voshchenkov, A. M.; Bokor, J.; Swartz, R. G.; and Ourmazd, A.; "High Performance 0.1-.mu.m Room Temperature Si MOSFETs", Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87, 1992.
Aoki, M.; Ishii, T.; Yoshimura, T.; Iiiyima, S., Yamanaka, T.; Kure, T.; Ohyu, K.; Shimohigashi, K.; "0.1 .mu.m CMOS Devices Using Low-Impurity Channel Transistors (LICT)", pp. 9.8.1-9.8.3, IEDM, 1987.
Yoshimura, Hisao; Matsuoka, Fumitomo; and Masakaru, Kakumu "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage", Semiconductor Device Engineering Laboratory, Japan, Proceedings of IEDM (1992), pp. 909-912.
Burr, James B, and Peterson, Allen M.; "Energy Considerations in Multichip-Module Multiprocessors", IEEE International Conference on Computer Design, pp. 593-600, 1991.
Burr, J. and Peterson, A.; "Ultra Low Power CMOS Technology", NASA VLSI Design Symposium, pp. 4.2.1-4.2.13, 1991.
Burr, Jim; "Stanford Ultra Low Power CMOS", Symposium Record, Hot Chips . V, pp. 7.4.1-7.4.12, Stanford, CA, 1993.
"A New Lease on Life for Old-Fashioned Chips", Business Week, Science and Technology, p. 100, Dec. 20, 1993.
Burr, James B., and Scott, John, "A 200 mV Self-Testing Encoder/Decoder using Stanford Ultra-Low Power CMOS", IEEE International Solid-State Circuits Conference, 1994.
Okumura, Yoshinori; Shirahata, Masayoshi; Hachisuka, Atsushi; Okudaira, Tomonori; Arima, Hideaki; and Matsukawa, Takayuki; "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", pp. 2541-2552, IEEE Transaction on Electron Devices, vol. 39, No. 11, Nov. 1992.
Sai-Halasz, George A.; Wordeman, Matthew R.; Kern, D.P.; Rishton, S.; and Ganin, E. "High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1 .mu.m Gate-Length Level", pp. 464-466, IEEE Electron Device Letters, vol. 9, No. 9, Sep. 1988.
Brassington Michael P.
Burr James B.
Mintel William
Sun Microsystems Inc.
LandOfFree
Low threshold voltage, high performance junction transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low threshold voltage, high performance junction transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low threshold voltage, high performance junction transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1786222