Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-11-22
2004-11-09
Tsai, H. Jey. (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06815223
ABSTRACT:
FIELD OF THE INVENTION
The invention in general relates to the fabrication of dielectric and ferroelectric metal oxides in integrated circuits, and in particular, to the formation of nonvolatile integrated circuit memories containing ferroelectric layered superlattice materials.
BACKGROUND OF THE INVENTION
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See U.S. Pat. No. 5,046,043 issued Sep. 3, 1991 to Miller et al. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102 issued Jul. 18, 1995 to Watanabe et al., and U.S. Pat. No. 5,468,684 issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits.
A typical ferroelectric memory in an integrated circuit contains a semiconductor substrate and a metal-oxide semiconductor field-effect transistor (MOSFET) electrically connected to a ferroelectric device, usually a ferroelectric capacitor. Layered superlattice materials currently in use and development comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen-containing gas at elevated temperatures. The individual heating steps in the presence of oxygen are typically performed at a temperature in the range of from 700° C. to 900° C. for 60 minutes to three hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700° C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226 issued Apr. 16, 1996, to Ito et al. Nevertheless, the total duration of annealing and other heating steps at 700° C. to 900° C. in methods disclosed in the prior art is typically in a range of about two to four hours or more, which may be economically unfeasible. More importantly, long exposure times of 30 minutes or more in oxygen, even at the somewhat reduced temperature ranges, typically results in oxygen damage to the semiconductor substrate and other elements of the CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen atoms from a thin film of metal oxide layered superlattice material tend to diffuse through the various materials contained in the integrated circuit and combine with atoms in the substrate and in semiconductor layers, forming undesired oxides. Undesired diffusion of oxygen is proportional to temperature and to the amount of time at elevated temperature. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby forming virtual capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor was placed on the side of the underlying CMOS circuit, and this reduced somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter “FET”), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor's bottom electrode and the underlying layers. The barrier layer not only must inhibit the diffusion of oxygen and other chemical species that may cause problems; it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. The maximum processing temperature tolerable with current barrier technology and fabrication methods is in a range of about 650° C. to 700° C. At temperatures in this range or higher for more than even a few minutes, the highest-temperature barrier materials quickly begin to degrade and to lose their diffusion-barrier properties. On the other hand, methods of forming layered superlattice materials disclosed in the prior art include heating the layered superlattice material and the associated memory stack in oxygen using RTP and furnace annealing (or in oxygen for part of the time, and in nonreactive gas part of the time) at temperatures in a range of about 650° C. to 800° C., for a minimum total duration of 60 minutes, but usually for two hours or longer. This prolonged heating at elevated temperature was done to achieve good crystallization of deposited layered superlattice materials. Nevertheless, such prolonged heating at elevated temperature typically damages semiconductor substrate, conductive plugs, diffusion barriers and other elements of integrated circuits.
It is common in the art to use rapid thermal processing (“RTP”) before furnace annealing to improve ferroelectric or dielectric properties of deposited metal oxide thin films, in particular, of layered superlattice materials. Methods using RTP before oxygen annealing are described in U.S. Pat. No. 5,648,114 issued Jul. 15, 1997 to Paz de Araujo et al., and U.S. Pat. No. 5,825,057 issued Oct. 20, 1998 to Watanabe et al. The RTP disclosed in the prior art is typically conducted at a temperature of 700° C. to 850° C. for a hold time of about 30 seconds, followed by an oxygen furnace anneal at 700-800° C. for 30 to 60 minutes, followed by a furnace post-anneal at 700-800° C. for 30 to 60 minutes in oxygen after formation of a top electrode and milling of the capacitor. In a variation, U.S. Pat. No. 6,326,315 B1 issued Dec. 4, 2001 to Uchiyama et al. teaches a ferroelectric anneal step in oxygen using an RTP-technique at 650° C. for 30 minutes, followed by a furnace post-anneal at 650° C. for 30 minutes in oxygen after formation of a top electrode and milling of the capacitor. Another approach of the prior art for making memory capacitors containing layered superlattice material is to conduct relatively low-temperature heating in oxygen (e.g., 600° C. or less) and higher-temperature heating in inert gas (e.g., in nitrogen at 800° C.). See, for example, U.S. Pat. No. 5,962,069 issued Oct. 5, 1999 to Schindler et al. Thus, these methods typically involve processing at elevated temperatures of 650° C. or higher for a minimum total duration in excess of 60 minutes.
Metal oxide materials, such as barium strontium titanate (“BST”) and other ABO
3
-type perovskites, are important for making integrated circuit thin film capacitors having high dielectric constants. Such capacitors are useful in fabricating integrated circuit memories, such as DRAMs. See for example, Kuniaki Koyama et al., “A Stacked Capacitor with (Ba
x
Sr
1-x
)TiO
3
For 256M DRAM” in IDEM (International Electron Devices Meeting) Technical Digest, December 1991, pp. 32.1.1-32.1.4, and U.S. Pat. No. 5,122,923, issued to Shogo Matsubara et al. PZT and PLZT compounds are ABO
3
-type perovskites having ferroelectric properties useful in ferroel
Celinska Jolanta
Joshi Vikram
Lim Myoungho
McMillan Larry D.
Paz de Araujo Carlos A.
Patton & Boggs LLP
Symetrix Corporation
Tsai H. Jey.
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