Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-25
2003-10-07
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S635000
Reexamination Certificate
active
06630713
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for bonding semiconductor articles and to a semiconductor article comprising bonded semiconductor articles.
BACKGROUND OF THE INVENTION
An increasing complexity of circuitry fabricated on and within semiconductor wafers has required greater complexity in the vertical structure of semiconductor wafers. For instance, early bipolar semiconductor devices were comprised of only two layers, typically deposited by chemical vapor deposition (CVD). These layers included an epitaxial layer and, for silicon wafers, a silicon dioxide passivation layer. Early metal-oxide-semiconductor (MOS) devices had only one silicon dioxide layer.
In contrast, more contemporary devices are constructed by utilizing a variety of very large scale integrated circuits (VLSI). The VLSI circuits are used in a solid state architecture divisible into two components—an instruction processor that supervises the order and decoding of instructions to be executed by the circuit and a data processor which performs the operations prescribed by the instructions on data. This complex: circuitry has required multiple levels of circuit interconnects positioned vertically, as well as horizontally, over several wafer layers. The layers are fabricated to perform functions such as conductors, semiconductors or insulators. The layers have been typically formed by deposition, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The complex circuitry has been fashioned from the layers utilizing sophisticated photo masking techniques.
One type of layer arrangement which has use in fabricating semiconductor devices, such as VLSI circuits, is a silicon layer positioned on an insulator (SOI) layer. This arrangement has been made by converting a top layer of a silicon wafer with a heavy oxygen implant to form an oxide. An epitaxial layer is grown on top of the oxide.
The SOI arrangement has also been made by bonding silicon wafers to each other. Bonded wafers have been fabricated to a thickness of five microns, with a resistivity in a range of 6 to 8 ohm-cm. The SOI structure permits layers of a semiconductor to be stacked using at least one insulating layer, a layer that bonds the layers together, and conductive interconnects or vertical busses extending through the insulating layer that are made utilizing a polymeric material such as an adhesive.
The annealed, bonded silicon wafers have been used to fabricate devices such as p-I-n diodes, power devices and micro mechanical structures. The annealed, bonded wafers have also been used to replace epitaxy fabrication. The annealed, bonded wafers have a versatility of thickness range which was not present in epitaxy fabrication in structures such as SOI structures.
With silicon wafer bonding and annealing, two flat silicon wafers, which are particle-free, are contacted to each other and bond with each other, chemically and physically. The wafer contact and physical bonding occur at ambient room temperature. The physically bonded wafers are annealed at an elevated temperature in order to increase bond strength by imparting a chemical bond to the wafers.
Q.-Y. Tong et al., in an article entitled “Hydrophobic Silicon Wafer Bonding” in
Applied Phys. Lett
., 64, No. 5, on Jan. 31, 1994, at pages 625 to 627, quantified the bond strength of wafers which had been bonded to each other at room temperature and annealed at an elevated temperature. Tong et al. showed that the bond strength increased by about two orders of magnitude from room temperature to 1100° C. Tong et al. studied both hydrophilic wafers and hydrophobic wafers and concluded that bonded hydrophobic wafers displayed superior performance, despite hydrogen bubble generation at the interface of the two bonded wafers. Tong et al. found that the bond energy at the wafer interface approached the fracture energy of bulk silicon at 700° C. and higher temperatures.
Gosele et al. in an article, “Self-Propagating Room Temperature Silicon Wafer Bonding in Ultrahigh Vacuum,” in
Appl. Phys. Lett
. in volume 67, No. 24, of Dec. 11, 1995 at pages 3614 to 3616, described a technique for minimizing the hydrogen bubble generation. Gosele et al. studied wafer bonding under high vacuum conditions. Gosele et al. demonstrated that four inch diameter hydrophobic wafers that were separately annealed at 600° to 800° C. in a vacuum to drive off hydrogen from the silicon surfaces when bonded at room temperature in vacuum achieved a uniform bubble-free bonded surface with a bond interface energy of bulk silicon.
The M. K. Weldon reference, “Physics and Chemistry of Silicon Wafer Bonding Investigated by Infrared Absorption and Spectroscopy,”
J. Vac. Sci. Technol. B
, 14(4), July/August 1996, pp. 3095-3105, described the surface phenomena of annealed silicon wafer surfaces. Wafers considered were hydrophilic wafers and hydrophobic wafers. Weldon et al. observed a shift in Si—H stretching frequency of bonded hydrophobic wafers due to van der Waals attraction. Hydrogen was driven off during annealing at high temperatures and Si—Si bonds were formed between the surfaces of the two annealed wafers.
Hydrophilic wafers had three to five monolayers of water and hydroxyl groups that terminated the silicon oxide layer formation at low temperature. With heating, the water groups dissociated, leading to the formation of additional silicon oxide. The hydroxyl groups subsequently disappeared resulting in the formation of Si—O—Si bridging linkages across the two surfaces of two wafers.
The fabrication technique of silicon wafer bonding and annealing has been confined to early stages of silicon wafer fabrication. In particular, the annealing is performed prior to any circuit or film fabrication. This limitation is necessary because of the high temperature required to anneal the wafers to each other. The annealing temperature range is high enough to damage or destroy elements or films of any integrated circuit that might be positioned on the wafers.
SUMMARY OF THE INVENTION
Embodiments of the present invention comprise a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing an article that has a semiconductor surface. The semiconductor surface of the article is contacted to a second semiconductor surface of a second article. The semiconductor surfaces are annealed with a pulsed energy source that imparts energy which is confined substantially to the semiconductor surfaces of each article and which is of such a short duration that only the semiconductor surfaces to be bonded are raised to the necessary annealing temperatures leaving opposite semiconductor surfaces at a temperature near the ambient temperature. The annealed surfaces are then contacted to each other and bonded to each other.
In another embodiment, the present invention also includes a semiconductor device comprised of two or more bonded semiconductor wafers. The bond of the semiconductor wafers is substantially free of defects. Any high temperature effects are confined to a region near the surfaces of the semiconductor wafers which have been annealed.
In one other embodiment, the present invention additionally includes a first silicon wafer and a second silicon wafer which is annealed and then bonded to the first silicon wafer. The second silicon wafer includes an element which is subject to change at the semiconductor annealing temperature. The element is kept free from any changes due to high temperature exposure as a result of the pulsed annealing method employed.
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Fahmy Wael
Micro)n Technology, Inc.
Peralta Ginette
Schwegman Lundberg Woessner & Kluth P.A.
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