Low temperature resist trimming process

Details Low temperature resist trimming process Low temperature resist trimming process

2002-05-23

2004-04-06

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S313000, C430S316000, C430S317000, C430S318000, C430S322000, C430S323000, C430S328000, C216S066000, C216S067000, C438S709000

Reexamination Certificate

active

06716570

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method of fabricating an integrated circuit in a microelectronic device or MEMS (micro-electromechanical) device. More particularly, the present invention is directed to the method of trimming the linewidth of photoresist which translates after etch transfer to shorter gate lengths in MOS transistors.
BACKGROUND OF THE INVENTION
One of the key steps in the manufacture of a Metal-oxide-semiconductor field effect transistor (MOSFET) is formation of a polysilicon or metal gate. The width of the gate conducting metal is typically one of the smallest dimensions in the device. To satisfy a constant demand for higher performance devices, the gate length or critical dimension (CD) which is actually measured as the width of a metal line is continually being reduced in each successive technology generation. For the 100 nm technology node that is currently being implemented in manufacturing, gate lengths as small as 60 or 70 nm are being produced. One shortcoming of state of the art lithography processes is that they are incapable of controllably printing features in photoresist smaller than about 100 nm. Many semiconductor manufacturers have overcome this problem using a trimming process which laterally shrinks the photoresist line with an etch step.
MOSFETs are typically made by first defining active areas in the substrate by forming isolation regions consisting of insulating material like silicon dioxide. The isolation regions can be generated by local oxidation of silicon (LOCOS) or by a shallow trench isolation (STI) technique. A gate oxide layer is grown over the substrate between the isolation regions. Then a gate electrode material such as polysilicon is deposited and patterned above the gate oxide layer. The gate length is determined by initially patterning a photoresist layer on the gate electrode layer. The openings in the photoresist are transferred through the gate layer by means of a plasma etch. Then ion implantation is used to form source/drain regions which define a channel length under the gate oxide. The final steps in making the device consist of adding sidewall spacers adjacent to the gate electrode, depositing an insulating layer on the substrate and forming contacts to the source/drain regions and to the gate electrodes.
The photoresist material which is patternwise exposed through a reticle can be either positive or negative tone. A positive tone photoresist undergoes a reaction in exposed regions that renders them soluble in a developing solution which is normally aqueous tetrabutyl ammonium hydroxide. Unexposed portions of the photoresist film remain insoluble in the developer. In negative photoresist, exposed regions are crosslinked or become otherwise insoluble in developer while the unexposed portions are washed away in aqueous base solution. Photoresist can be applied as a single layer material or part of a bilayer system. In bilayer applications, the pattern formed in a thin imaging layer is etch transferred through a thicker underlayer that is used for its planarization and anti-reflective properties. In some cases, a single layer photoresist is selected which is very opaque to the incident exposing radiation such that only a top portion near the surface absorbs energy that causes a chemical change to occur. Top surface imaging techniques are frequently combined with a silylation process which forms O—Si bonds selectively in either the exposed or unexposed regions. A subsequent oxygen etch removes photoresist in regions that are not protected by the O—Si bonds in the film. Thermal stability of photoresist features are typically in the range of 90° C. to 150° C. Any processes including plasma etches that involve temperatures in this range or above the thermal stability limit will cause the resist to flow and distort.
The lithography process used to pattern the photoresist above the gate layer generally involves exposure tools which use wavelengths that are selected from a range of 450 nm to sub-200 nm. High throughput projection electron beam tools that have the capability of imaging 50 to 70 nm resist features are still in development and are too expensive to implement. X-ray and ion beam imaging systems have also been used to image photoresist but in general are not found in high volume manufacturing lines. Even with the most advanced exposures tools, phase shift reticles, and resolution enhancement techniques that are currently available in manufacturing, the minimum feature size that can be reliably imaged in a photoresist is about 100 nm. This size is not small enough to meet the demand for sub-100 nm gate lengths for most new devices. As a result, the industry has resorted to other methods that require trimming the pattern in the masking layer that is subsequently etch transferred to form the gate electrode.
The process of accurately and repeatedly etching patterns has been the subject of significant development, especially in the area of semiconductor electronics. The extent to which integrated circuits can be miniaturized depends on the accuracy and reliability of the patterning and etching processes. The etching process involves the use of a mask to selectively allow an etchant to remove underlying semiconductor or conductive material that has been exposed through openings in the mask pattern. Although wet etchants can be employed, a dry plasma etch is usually preferred when the mask is a patterned photoresist layer.
One of the original methods of MOS device fabrication involving gate lengths less than 200 nm is published in IEEE Electron Device Letters, Vol. 9, No. 4, pp. 186-188 (1988) by C. Hu. A plasma etching system with an O
2
pressure of 300 mTorr and RF power of 50 Watts was used to laterally trim a photoresist feature before an etch transfer into an underlying polysilicon layer. Oxygen radicals react with elements of C, H, N, and S in the photoresist to form their corresponding oxides such as CO
2
, H
2
O, NO
2
and SO
2
which are swept away in the exhaust stream.
A more recent publication by M. Ono in J. Vacuum. Sci. Tech. B, Vol. 13, 1740-1743 (1995) mentions the use of oxygen plasma ashing to achieve 40 nm gate electrodes. The lateral trimming is about 15 nm/min. and is almost independent of the original photoresist dimension which varies from 216 to 324 nm in width.
Besides the lateral erosion of the photoresist image, some top loss can also occur during the trimming process which is unacceptable if there is not enough resist thickness remaining to serve as a mask for the subsequent etch into the polysilicon layer. The vertical trim rate of a photoresist image can be more than twice as fast as the horizontal trim rate. Jeon et al. in J. Vacuum Science Tech. B, Vol. 12, pp., 2800-2804 (1994), utilize a Deep Ultraviolet (UV) hardening with wavelengths near 300 nm to harden the photoresist after a trimming step and then proceed with etch transfer into an underlying hard mask. The hard mask (silicon nitride) then becomes a mask for etching polysilicon gates. The photoresist in this example is patterned with i-line (365 nm) imaging and contains novolac resin which becomes crosslinked in the hardening mechanism. However, other resists such as those imaged by Deep UV (248 nm) radiation which contain polyvinyl phenol polymers can be crosslinked or hardened as well. The particular wavelengths selected for hardening depend on their absorbance in the photoresist film. A high absorbance will cause a hardening in only the outer skin while a low absorbance will result in too little energy being absorbed by the film and an excessively prolonged hardening process.
In some cases a bottom anti-reflective coating (BARC) is formed on the gate layer prior to the photoresist coating in order to control reflectivity during the photoresist patterning process. This leads to a tighter control of dimensions in the printed pattern. In U.S. Pat. No. 5,804,088, a TiN BARC also functions as a hard mask for the polysilicon etch step. U.S. Pat. No. 6,010,829 describes the use of an organic BARC which is isotropicall

Affiliated with

Also associated with

Rating

Low temperature resist trimming process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low temperature resist trimming process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low temperature resist trimming process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3240796