Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2003-02-24
2004-11-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C257S295000
Reexamination Certificate
active
06815224
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing ferroelectric strontium bismuth tantalate (SBT), to a method for fabricating a ferroelectric storage capacitor which includes a ferroelectric SBT layer of this type, to a semiconductor memory which includes the storage capacitor, and to a method for fabricating a semiconductor transistor which includes a ferroelectric SBT layer. In the strontium bismuth tantalate material, the tantalum content can be at least partially replaced by the element niobium.
In the semiconductor industry, in particular the silicon industry, it is now known to use ferroelectric or paraelectric materials for various purposes. Layers of this type can be used as replacements for the dielectric, which normally consists of an oxide or nitride layer, of a storage capacitor of a DRAM (Dynamic Random Access Memory) semiconductor memory. The advantage of these “FeRAMs” is: first the much higher dielectric constant of the ferroelectric material, and second the possibility of fabricating a nonvolatile memory module by the remanent polarization of the ferroelectric material.
Furthermore, in the case of MOS transistors, a ferroelectric layer can be formed as a replacement for the gate oxide layer as an insulating layer between the gate electrode and the channel section of the semiconductor surface, with the result that a nonvolatile memory transistor can be fabricated.
Strontium bismuth tantalate, with a composition SrBi
2
Ta
2
O
9
(SBT) or SrBi
2
(Ta, Nb)
2
O
9
(SBTN) has been known for some time as a ferroelectric material and can be deposited on a substrate, for example, by using a metal organic deposition process (MOCVD, MOD). However, the SBT/SBTN is generally not deposited in the ferroelectric phase, but rather is only converted into the ferroelectric phase by a subsequent heat treatment, known as the ferro-anneal, in an oxygen-containing atmosphere. The temperatures required for this heat treatment step according to the methods that have been disclosed hitherto are above 700° C. For this reason, inert electrode materials, such as for example, platinum metals and conductive oxides thereof, have to be used to fabricate storage capacitors from this ferroelectric material.
To build up a DRAM memory cell, there are substantially two different structural concepts. A common feature of the two different structural concepts is that the switching transistor is formed in a lower level directly on the semiconductor substrate and the storage capacitor is arranged in a higher level. The switching transistor and the storage capacitor are separated from one another by an insulation layer that is positioned between them. According to a first structural concept (stacked cell), the switching transistor and the storage capacitor are arranged substantially directly above one another, and the lower electrode of the storage capacitor is electrically connected to the drain region of the MOS transistor by a contact hole (plug) which has been formed in the insulation layer and filled with a conductive material. According to a second structural concept (offset cell), the switching transistor and the storage capacitor are arranged offset with respect to one another, and the upper electrode of the storage capacitor is electrically connected to the drain region of the MOS transistor through two contact holes.
On account of the considerably smaller amount of space required by the “stacked cell” concept, this would under normal circumstances have to be preferred to the “offset cell” concept. However, the difficulty of the former concept is the need to arrange a diffusion barrier between the contact hole that has been filled with polycrystalline silicon or tungsten and the lower electrode, which usually consists of platinum, of the storage capacitor.
FIG. 1
shows a DRAM memory cell which uses the “stacked cell” concept. First of all, a MOS transistor
10
is fabricated on a semiconductor substrate
1
by forming a drain region
11
and a source region
12
by doping. A channel
13
is located between them. The conductivity of this channel can be controlled by a gate
14
, which is arranged above the channel
13
. The gate
14
may be formed by or connected to a word line of the memory component. The source region
12
is connected to a bit line of the memory component. The MOS transistor
10
is then covered with a planarization insulation layer
15
, usually of an oxide such as SiO
2
. A storage capacitor
20
, which substantially includes a lower electrode layer
21
, a ferroelectric layer
22
and an upper electrode layer
23
, is formed on this insulation layer
15
. The lower electrode layer
21
is arranged above a contact hole
30
, which is filled with a conductive material, such as polycrystalline silicon, and is connected to the drain region
11
of the switching transistor
10
by this contact hole. Between the lower electrode layer
21
and the contact hole
30
there is a diffusion barrier layer
25
, which on the one hand prevents Si material from diffusing out of the contact hole
30
into the ferroelectric layer
22
and on the other hand prevents Bi/Bi
2
O
3
and oxygen from diffusing out of the ferroelectric layer
22
into the contact hole
30
. In particular the latter phenomenon may cause partial oxidation of the silicon of the contact hole
30
, so that a nonconductive SiO
2
layer is formed. Since the lower electrode layer
21
usually consists of platinum, which has a columnar grain structure, this platinum layer forms only an inadequate barrier to these diffusion phenomena.
Diffusion barriers are often formed from titanium layers or Ti/TiN double layers. However, it is known that these are unable to withstand a process temperature above 700° C., as required in conventional methods for producing the ferroelectric layer
22
. Hitherto, there has been no technologically established diffusion barriers which are suitable for such high process temperatures.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing ferroelectric strontium bismuth tantalate which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the present invention to provide a method for producing ferroelectric strontium bismuth tantalite, which can be integrated in a process for fabricating a component, such as a storage capacitor, and does not cause damage to other existing materials. In particular, it is also an object of the present invention to provide a method of this type in which the heat treatment step can be carried out at a lower temperature than that used in the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing ferroelectric Sr
x
Bi
y
Ta
2
O
9
(SBT) or Sr
x
Bi
y
(Ta, Nb)
2
O
9
(SBTN). The method includes steps of: depositing Sr
x
Bi
y
Ta
2
O
9
(SBT) or Sr
x
Bi
y
(Ta, Nb)
2
O
9
(SBTN) on a substrate, where 0.7≦x≦1 and 2.1≦y≦3.0; and performing a heat treatment step at a temperature T
1
being less than 700° C., until the Sr
x
Bi
y
Ta
2
O
9
(SBT) or the Sr
x
Bi
y
(Ta, Nb)
2
O
9
(SBTN) has adopted a ferroelectric phase.
In accordance with an added feature of the invention, after performing the heat treatment step, which defines a first heat treatment step, performing a second heat treatment step at a temperature T
2
, where 550° C.≦T
2
≦700° C.; and simultaneously with performing the second heat treatment step, removing bismuth that evaporates from the Sr
x
Bi
y
Ta
2
O
9
(SBT) or the Sr
x
Bi
y
(Ta, Nb)
2
O
9
(SBTN) during the second heat treatment step by pumping out the bismith.
In accordance with an additional feature of the invention, when performing the step of depositing the Sr
x
Bi
y
Ta
2
O
9
(SBT) or the Sr
x
Bi
y
(Ta, Nb)
2
O
9
(SBTN) on the substrate, insuring that y≧2.4; and when performing the heat treatment step, insuring that T
1
≦660° C.
In accordance with another feature of the invention, the met
Bachhofer Harald
Haneder Thomas
Spindler Oswald
Waser Rainer
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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