Low temperature process to locally form high-k gate dielectrics

Details Low temperature process to locally form high-k gate dielectrics Low temperature process to locally form high-k gate dielectrics

2001-02-09

2002-12-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S584000

Reexamination Certificate

active

06495437

ABSTRACT:

FIELD OF THE INVENTION
The present specification relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present specification relates to a method of manufacturing integrated circuits having transistors with high-k gate dielectrics.
BACKGROUND OF THE INVENTION
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit (ULSI) can include over 1 million transistors.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension (shallow source and drain extensions) that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to a conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the silicon dioxide spacers. After doping, the source and drain regions are annealed in a high temperature process to activate the dopants in the source and drain regions.
High temperature processes over 750 to 800° C. can cause dielectric materials with a high dielectric constant (k) to react with the substrate (e.g., silicon). High-k (k>20) gate dielectrics are desirable as critical transistor dimensions continue to decrease. The reduction of critical transistor dimensions requires that the thickness of the gate oxide also be reduced. A major drawback to the decreased gate oxide thickness (e.g., <30 Å) is that direct tunneling gate leakage current increases as gate oxide thickness decreases. To suppress gate leakage current, material with a high dielectric constant (k) can be used as a gate dielectric instead of the conventional gate oxides, such as thermally grown silicon dioxide.
High-k gate dielectric materials have advantages over conventional gate oxides. A high-k gate dielectric material with the same effective electrical thickness (same capacitive effect) as a thermal oxide is much thicker physically than the conventional oxide. Being thicker physically, the high-k dielectric gate insulator is less susceptible to direct tunnel leakage current. Tunnel leakage current is exponentially proportional to the gate dielectric thickness. Thus, using a high-k dielectric gate insulator significantly reduces the direct tunneling current flow through the gate insulator.
High-k dielectric materials include, for example, aluminum oxide (Al
2
O
3
), titanium oxide (Ti
2
O
3
), silicon nitride (Si
3
N
4
) and tantalum pentaoxide (TaO
5
). Aluminum oxide has a dielectric constant (k) equal to eight (8) and is relatively easy to make as a gate insulator for a very small transistor. Small transistors often have a physical gate length of less than 80 nm.
Silicidation processes can adversely affect high-k gate dielectric materials of the gate stack. Silicidation processes often utilize high temperature deposition on low temperature deposition combined with a heating step. For example, silicidation processes, such as, cobalt silicidation processes, often require temperatures of 800-825° C. which can cause the high-k gate dielectric material to react with the substrate or the gate conductor.
Thus, there is a need for transistors manufactured in an optimized silicidation process. Yet further, there is a need for a transistor with elevated source and drain regions and a high-k gate dielectric. Yet even further, there is a need for a process of forming a transistor with silicided source and drain regions and a high-k gate dielectric. Further, there is a need for a process flow which forms high-k gate dielectric films after silicidation of drain and source regions. Even further, there is a need for a process that utilizes a high temperature (greater than 750° C.) silicidation technique and a high-k gate dielectric layer. Even further still, there is a need for a method of forming a high-k gate dielectric layer after source and drain silicidation.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of forming a dielectric insulator for a transistor. The method includes providing a sacrificial gate structure on a substrate, forming source/drain regions, siliciding the source/drain regions, removing the sacrificial gate material, and transforming metal material into a high-k gate dielectric material for the dielectric insulator. The gate structure includes the layer of metal material above the substrate. The gate structure also includes the sacrificial gate material above the metal material.
Another exemplary embodiment relates to a method of manufacturing integrated circuit. The method includes providing a gate structure, providing a silicide layer next to at least one side of the gate structure, removing a sacrificial layer in the gate structure, and forming a dielectric gate insulator. The dielectric gate insulator is formed from a metal layer associated with the gate structure.
Yet another exemplary embodiment relates to a method of forming a gate structure. The gate structure includes a high-k dielectric layer. The method includes the following steps in the following order: depositing a metal layer above a substrate, depositing a sacrificial layer above the metal layer, etching the sacrificial layer and the metal layer, siliciding the substrate, removing the sacrificial layer, and forming the high-k dielectric layer using the metal layer. The etching of the sacrificial and the metal layer defines the gate structure. The sacrificial layer is removed from the gate structure. The high-k gate dielectric layer is formed within the gate structure.


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