Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-06-07
2002-04-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000, C438S790000, C427S255370, C427S490000
Reexamination Certificate
active
06365528
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly this invention relates to the low temperature formation of a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for use in the formation of integrated circuit structures.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
Dobson et al., in an article entitled “Advanced SiO
2
Planarization Using Silane and H
2
O
2
”, published in Semiconductor International, December 1994, at pages 85-88, describe the low temperature formation of SiO
2
by reaction of silane (SiH
4
) with hydrogen peroxide (H
2
O
2
) to produce a silicon oxide which flows like a liquid and thus exhibits good gap fill characteristics.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Flowfill process.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on February 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
The incorporation of such carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. The carbon doped silicon oxide materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
While such carbon-doped silicon oxide dielectric materials do exhibit the desired low k (i.e., dielectric constants below about 3.0) resulting in reduced capacitance of the dielectric material, a major problem of such carbon-doped silicon oxide is a low resistance to oxidation that results in a destruction of the incorporated hydrocarbons and a resulting increase in the overall dielectric constant of the dielectric material. The removal of the methyl group results in a more hydrophilic surface that is responsible for a so-called “via poisoning” which is observed after via etch and photoresist strip with oxygen-containing plasma, and is related to suppression of the surface nucleation in subsequent via liner deposition steps.
More recently, Sugahara et al., in an article entitled “Chemical Vapor Deposition of CF
3
-incorporated Silica Films for Interlayer Dielectric Applications”, published in the 1999 Joint International Meeting, Electrochemical Society Meeting Abstracts, volume 99-2, Abstract 746, 1999, described the deposition of a CF
3
-incorporated silicon oxide by the reaction of trimethyl-fluoromethyl-silane with an ozone oxidizer at an elevated temperature. The authors reported that the reactivity of the Si-alkyl bonds is very low, and thus ozone was used as an oxidizer for the Si-alkyl bonds in a hot-wall-type reactor with a wall temperature of 350° C. The strong resistance to oxidation of such a material makes it possible to avoid the “via poisoning” of carbon doped silicas and to prevent loss in low k-value during conventional via etching and photoresist strip processing with oxygen-containing plasma. On the other hand, it is known that dielectric films produced by high temperature ozone processes are characterized by poor gap-fill, while continuous shrinkage in feature size of integrated circuit structure demands an increased gap-fill capability.
It would, therefore, be desirable to provide a low k silicon oxide dielectric material which would exhibit the gap-fill properties and film adherence properties of CVD-formed low k carbon doped silicon oxide dielectric materials such as discussed by the Dobson et al., Peters, and McClatchie et al. articles discussed above, while also exhibiting properties of better resistance to oxidation during conventional via etch and subsequent photoresist removal with oxygen-containing plasma, such as attributed to the high temperature-formed CF
3
-incorporated silica films reported by Sugahara et al.
SUMMARY OF THE INVENTION
In accordance with the invention, a low temperature process is provided for forming a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for integrated circuit structures which comprises providing a reactor having a semiconductor substrate mounted on a substrate support which is maintained at a low temperature, and forming on the surface of the substrate a low k fluorine and carbon-containing silicon oxide dielectric material by reacting together a vaporous source of a mild oxidizing agent such as a peroxide and a vaporous substituted silane having the formula (CF
m
H
n
)—Si—(R)
x
H
y
wherein is 1-3; n is 3-m; R is an alkyl selected from the group consisting of ethyl (—C
2
H
5
), methyl (—CH
3
), and mixtures thereof; x is 1-3; and y is 3-x.
REFERENCES:
patent: 3652331 (1972-03-01), Yamazaki
patent: 4771328 (1988-09-01), Malaviya et al.
patent: 5314845 (1994-05-01), Lee et al.
patent: 5364800 (1994-11-01), Joyner
patent: 5376595 (1994-12-01), Zupancic et al.
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5558718 (1996-09-01), Leung
patent: 5559367 (1996-09-01), Cohen et al.
patent: 5580429 (1996-12-01), Chan et al.
patent: 5628871 (1997-05-01), Shinagawa
patent: 5675187 (1997-10-01), Numata et al.
patent: 5688724 (1997-11-01), Yoon et al.
patent: 5864172 (1999-01-01), Kapoor et al.
patent: 5874367 (1999-02-01), Dobson
patent: 5915203 (1999-06-01), Sengupta et al.
patent: 5939763 (1999-08-01), Hao et al.
patent: 6025263 (2000-02-01), Tsai et al.
patent: 6028015 (2000-02-01), Wang et al.
patent: 6037248 (2000-03-01), Ahn
patent: 6043167 (2000-03-01), Lee et al.
patent: 6051073 (2000-04-01), Chu et al.
patent: 6051477 (2000-04-01), Nam
patent: 6066574 (2000-05-01), You et al.
patent: 6114259 (2000-09-01), Sukharev et al.
patent: 6147012 (2000-11-01), Sukharev et al.
patent: 6153524 (2000-11-01), Henley et al.
patent: 6204192 (2001-03-01), Zhao et a
Sukharev Valeriy
Zubkov Vladimir
LSI Logic Corporation
Lytle Craig P.
Smith Matthew
Taylor John P.
LandOfFree
LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2833729