Low temperature plasma strip process

Details Low temperature plasma strip process Low temperature plasma strip process

2000-03-24

2002-07-02

Goudreau, George (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001300, C438S715000, C438S725000, C216S049000, C216S067000

Reexamination Certificate

active

06412498

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of manufacturing semiconductor devices with patterned metal interconnections, and more particularly, to manufacturing high density semiconductor devices with submicron patterned metal features for local and global interconnections.
BACKGROUND OF THE INVENTION
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components, such as transistors comprising gates and source/drain regions, are formed and interconnected. In one interconnection scheme, shown in FIGS.
1
(
a
) and
1
(
b
), source/drain regions
3
and gates
4
of neighboring transistors are connected to one another by local interconnections
5
to form “standard cells” which, in turn, are connected to each other locally and globally by several patterned metal layers (e.g.
8
) interleaved with insulating layers (e.g.
7
) formed above and extending substantially horizontally with respect to the substrate
1
surface. The metal layers (e.g.
8
) are connected to one another and to the local interconnection
5
by vias (e.g., contacts
6
).
Conventional practices employ aluminum alloys for interconnects, with various metals, such as copper, added for electromigration improvement. One conventional interconnect scheme, shown in FIG.
1
(
a
), comprises depositing a composite three-layer metal stack
8
comprising an upper layer
8
c
of titanium nitride (TiN) or titanium-titanium nitride (Ti—TiN), an intermediate layer
8
b
of aluminum (Al) or Al alloy and a lower layer
8
a
of titanium (Ti) or Ti—TiN, as by sputtering.
A patterned photoresist mask
9
is then formed on the metal layer
8
defining a metal pattern and the underlying metal is etched through the mask
9
to form the pattern of metal lines
8
. The quality of the photoresist mask
9
is crucial to the definition of the metal interconnect layer and, ultimately, to device performance. Thus, if defects are observed or detected in the mask, it must be removed and replaced (i.e., reworked) with a defect free mask before etching. A successful resist mask rework completely removes all of the resist
9
without damaging the underlying substrate material, increasing the defect density, or introducing systematic yield variations.
Conventional photoresist mask removal techniques include pumping down the pressure in a plasma chamber after the wafer has been placed on a heated platen and stripping the wafer, such as by oxygen plasma stripping, while the wafer temperature is substantially at the platen temperature of 240° C. to 260° C. The stripping process is typically followed by solvent cleaning. A new patterned photoresist mask is then formed on the underlying metal layer and etching is conducted to form the patterned metal lines. However, wafers processed by these conventional techniques exhibit an abnormally high defect density after the subsequent metal etch process, due to formation of a residue (R). This residue (R), illustrated in FIG.
1
(
b
), causes bridging between adjacent lines and, hence, short-circuiting and device failure.
Investigation by the inventors revealed that residue (R) was formed as a result of precipitates from an alloy solution, influenced by the temperature and duration of the rework. In one exemplary configuration, copper (Cu) precipitated out of an Aluminum-Copper (Al/1%Cu) alloy, leading to residue formation and bridging, and the residue (R) increased as the concentration of the copper in the AlCu alloy was increased. Moreover, the residue (R) was found to increase and decrease with increases and decreases in the temperature and duration of the rework.
Generally, a method is needed to permit efficient limitation of wafer temperature during processing to prevent formation of the aforementioned precipitates. More specifically, there is a need for a method enabling replacement of a defective resist mask without the aforementioned bridging yield losses and without collaterally compromising throughput or yield. These needs are particularly acute in manufacturing high density devices having minimal inter-wiring spaces.
SUMMARY OF THE INVENTION
The inventors determined that the wafer temperature should be decreased below approximately 210° C. to prevent residue formation, contrary to conventional plasma strip operations which seek to raise the wafer temperature as high as possible to increase the strip rate. The inventors also determined that the rate of heat transfer between the platen and the wafer corresponded to increases and decreases of the chamber pressure when the wafer contacted the platen.
One approach to limiting wafer temperature is to lower the platen temperature in the plasma strip chamber. However, this temperature change is time consuming, lowering throughput, and potentially can increase the defect levels in the chamber, lowering yield.
According to the invention, the earlier stated needs are met in part by a method for plasma stripping a resist from a wafer, including the steps of locating a wafer in a chamber having a platen and reducing a pressure in the chamber to a predetermined pressure. The wafer is placed in contact with the platen and heated to a temperature below approximately 210° C. While the temperature is below approximately 210° C., the wafer is moved away from the platen and plasma stripping is performed on a resist layer with the temperature of the wafer being maintained below approximately 210° C.
Another aspect of the invention includes a method for manufacturing a semiconductor device, including the steps of placing a wafer in a chamber having a platen and conducting a fast heating by placing the wafer in contact with the platen to heat the wafer to within a first temperature range between approximately 150° C. and 180° C. Then, a slow heating is conducted by raising the wafer away from the platen to heat the wafer to within a second temperature range between approximately 180° C. and 210° C. Plasma stripping of a resist layer is performed while the wafer temperature is maintained within approximately 150° C. and 180° C. The separate fast and slow heating of the wafer results in a more desirable controlled heating of the wafer during resist stripping is achieved.
Maintaining the wafer temperature below approximately 210° C. during the plasma stripping process in accord with the above aspects of the invention, residue (R) formation is prevented, improving product yield.
Additional features and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 4624728 (1986-11-01), Bithell et al.
patent: 4689112 (1987-08-01), Bersin
patent: 5226056 (1993-07-01), Kikuchi et al.
patent: 5228052 (1993-07-01), Kikuchi et al.
patent: 5681780 (1997-10-01), Mihara et al.
patent: 5811358 (1998-09-01), Tseng et al.
patent: 5882489 (1999-03-01), Bersin et al.
patent: 5939241 (1999-08-01), Leu et al.
patent: 6044850 (2000-04-01), Ozawa et al.
patent: 6251794 (2001-06-01), Peng et al.
patent: 01-179327 (1989-07-01), None
patent: 06-124926 (1994-05-01), None
patent: 08-288260 (1996-11-01), None
patent: 09-027474 (1997-01-01), None
patent: 10-135186 (1998-

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